Driving apparatus and control method for electric actuator
    1.
    发明授权
    Driving apparatus and control method for electric actuator 有权
    电动执行机构驱动装置及控制方法

    公开(公告)号:US08355235B2

    公开(公告)日:2013-01-15

    申请号:US11052244

    申请日:2005-02-08

    IPC分类号: H01H47/00

    CPC分类号: F01L1/34 F01L13/00

    摘要: A plurality of reference signals output from a controller which computes an operation amount of an electric actuator is subjected to the logical operation, and the power supply to a drive circuit for the electric actuator is shut off based on an output by the logical operation.

    摘要翻译: 从计算电致动器的操作量的控制器输出的多个参考信号经历逻辑运算,并且基于逻辑运算的输出关闭到用于电致动器的驱动电路的电力供给。

    Apparatus and method for controlling valve timing of an engine
    2.
    发明授权
    Apparatus and method for controlling valve timing of an engine 有权
    用于控制发动机气门正时的装置和方法

    公开(公告)号:US06505585B1

    公开(公告)日:2003-01-14

    申请号:US09570464

    申请日:2000-05-12

    IPC分类号: F01L134

    摘要: In a vane type valve timing control apparatus, when an amplitude of a rotation phase of a cam shaft with respect to a crank shaft is above a predetermined value, a target value for the rotation phase is forcibly changed to a maximum advance angle and a maximum delay angle, so that oil of an advance angle side hydraulic chamber and a delay angle side hydraulic chamber is discharged together with air.

    摘要翻译: 在叶片式气门正时控制装置中,当凸轮轴相对于曲轴的旋转相位的振幅高于预定值时,旋转相位的目标值被强制地改变为最大提前角和最大值 延迟角度,使得提前角侧液压室和延迟角侧液压室的油与空气一起排出。

    Apparatus and method prohibiting RAM diagnosis when other units may access RAM
    3.
    发明授权
    Apparatus and method prohibiting RAM diagnosis when other units may access RAM 有权
    当其他单元可能访问RAM时,装置和方法禁止RAM诊断

    公开(公告)号:US06295589B1

    公开(公告)日:2001-09-25

    申请号:US09374511

    申请日:1999-08-16

    IPC分类号: G06F1200

    CPC分类号: G06F11/004 G06F11/22

    摘要: Erroneous diagnosis caused by a case where hardware other than an ALU (arithmetical and logic unit) has a function to access a RAM directly due to the construction of a CPU is to be prevented. In order to do so, interrupt is prohibited at every predetermined diagnosis timing. Then, determination is made as to whether a start-up of a DMAC (direct memory access controller) is approved or not, and only when the start-up is not approved, the diagnosis is performed to a diagnosis object RAM by previously determined diagnosis unit bytes at a time through a read/write method. When failure of the RAM is determined, the diagnosis procedure is advanced to an NG process. When the start-up of the DMAC is approved, the diagnosis of the diagnosis object RAM is prohibited, and the address of the object RAM is stored in a memory so that the object RAM is diagnosed at a next diagnosis timing.

    摘要翻译: 可以防止由于ALU(算术逻辑单元)以外的硬件具有由于CPU的构造而直接访问RAM的功能引起的错误诊断。 为了这样做,在每个预定诊断定时禁止中断。 然后,确定DMAC(直接存储器存取控制器)的启动是否被批准,并且仅当启动不被批准时,通过预先确定的诊断对诊断对象RAM执行诊断 通过读/写方法一次单位字节。 当确定RAM的故障时,将诊断程序提前到NG过程。 当DMAC的启动被批准时,禁止诊断对象RAM的诊断,并且将对象RAM的地址存储在存储器中,使得在下一个诊断定时诊断对象RAM。

    Control apparatus of direct injection spark ignition type internal
combustion engine
    6.
    发明授权
    Control apparatus of direct injection spark ignition type internal combustion engine 失效
    直喷式火花点火式内燃机控制装置

    公开(公告)号:US5983854A

    公开(公告)日:1999-11-16

    申请号:US106761

    申请日:1998-06-30

    摘要: The present invention securely prevents the erroneous switching of the combustion mode to the stratified charge combustion, and avoids deterioration of the driving performance. In order to do so, apart from a software determination device inside a main CPU for performing the permission determination on the switching to the stratified charge combustion based on an input signal related to the engine drive condition, a hardware detection circuit (gate array) is equipped for performing the permission determination on the switching to the stratified charge combustion mode based on the input signal related to the engine drive condition. The main CPU is equipped with a combustion mode order device for finally ordering the stratified charge combustion by permitting the switching to the stratified charge combustion only when the two permission determinations both permit the switching to the stratified charge combustion. Further, a sub CPU is mounted which is equipped with a fail-safe device for based on the final permission determination from the main CPU and the permission determination from the hardware determination device, performing a fail-safe process when the two determinations are inconsistent.

    摘要翻译: 本发明可以可靠地防止燃烧模式向分层充气燃烧的错误切换,避免驱动性能的劣化。 为了这样做,除了主CPU内的软件确定装置,基于与发动机驱动条件相关的输入信号来执行对分层充电燃烧的切换的许可确定,硬件检测电路(门阵列)是 基于与发动机驱动条件相关的输入信号,进行对分层充气燃烧模式切换的允许判定。 主CPU配备有燃烧模式订单装置,用于最终订购分层充气燃烧,只有当两个允许确定都允许切换到分层充气燃烧时,允许切换分层充气燃烧。 此外,安装有基于来自主CPU的最终许可确定的故障安全装置和来自硬件确定装置的许可确定的子CPU,当两个确定不一致时执行故障安全进程。

    Control device
    7.
    发明授权

    公开(公告)号:US10712716B2

    公开(公告)日:2020-07-14

    申请号:US14768635

    申请日:2014-02-12

    IPC分类号: G05B11/42 G05B17/02 G05B11/36

    摘要: A control device according to the present invention includes a plurality of arithmetic units that operate in parallel. A sensor value of the control amount is input to the first arithmetic unit in a signal transmission sequence, and a correction amount for the manipulation amount is output from the last arithmetic unit in the signal transmission sequence. The first arithmetic unit has a controller that produces an output by processing the input sensor value, and the arithmetic units other than the first arithmetic unit has a delay element that delays an input by a predetermined number of steps and a controller that produces an output by processing the delayed input.

    Control device design method and control device

    公开(公告)号:US10180669B2

    公开(公告)日:2019-01-15

    申请号:US14768606

    申请日:2014-02-12

    IPC分类号: G05B17/02

    摘要: The present invention relates to a control device design method for a control device that determines a manipulation amount of a control object having a dead time by feedback control so as to bring a control amount of the control object closer to a target value. The method according to the present invention includes a step of designing a feedback loop that computes a correction amount for the manipulation amount using a plurality of controllers including a prediction model of the control object, a step of deriving the same number of delay elements as the plurality of controllers from a dead time element of the prediction model, and a step of allocating the plurality of controllers associated with the delay elements to a plurality of arithmetic units so that the computation of the feedback loop is performed by parallel computation by the plurality of arithmetic units that operate in parallel.

    PARALLEL COMPUTING DEVICE
    9.
    发明申请
    PARALLEL COMPUTING DEVICE 审中-公开
    并行计算设备

    公开(公告)号:US20150277988A1

    公开(公告)日:2015-10-01

    申请号:US14436164

    申请日:2012-10-18

    IPC分类号: G06F9/50 G06F1/32

    摘要: The present invention relates to a multi-core parallel computing device that repeatedly processes a plurality of tasks having a restricted processing completion time using one or more cores having a variable operation frequency. When activating a new core and allocating the plurality of tasks to the new core and an operating core, the parallel computing device according to the present invention increases the operation frequency of the operating core.

    摘要翻译: 本发明涉及一种多核并行计算设备,其使用具有可变操作频率的一个或多个核心重复处理具有受限处理完成时间的多个任务。 当激活新核心并将多个任务分配给新核心和操作核心时,根据本发明的并行计算设备增加了操作核心的操作频率。

    ENGINE CONTROL DEVICE
    10.
    发明申请

    公开(公告)号:US20150081101A1

    公开(公告)日:2015-03-19

    申请号:US14347025

    申请日:2011-09-28

    申请人: Satoru Watanabe

    发明人: Satoru Watanabe

    IPC分类号: F01B25/00 G05B15/02

    摘要: It is a task of the invention to make it possible to calculate a control target value of one actuator or control target values of a plurality of actuators regarding engine control at a high speed through the use of a multicore processor. With a view to accomplishing this task, a plurality of lattice points that are arranged on a two-dimensional orthogonal coordinate system having axes representing a first operating condition and a second operating condition respectively are associated respectively with at least one or some of a plurality of cores that are arranged in a latticed manner on the multicore processor on one-on-one level on a same line as on the two-dimensional orthogonal coordinate system, and a calculation program for calculating an optimal control value at the associated lattice point or calculation programs for calculating optimal control values at the associated lattice points are allocated respectively to at least one or some of the plurality of the cores. In addition, each of the cores with which the lattice points are associated respectively is programmed, in a case where an operation area on the two-dimensional orthogonal coordinate system to which a current operating point belongs is an area that is defined by the lattice point associated with each of the cores itself, to transmit, to an interpolation calculation core, an optimal control value at the relevant lattice point that is calculated by each of the cores itself. The interpolation calculation core is programmed to perform an interpolation calculation of an optimal control value at the current operating point using optimal control values at all the lattice points that define the operation area on the two-dimensional orthogonal coordinate system to which the current operating point belongs. In addition, the multicore processor outputs the optimal control value at the current operating point, which is obtained from the interpolation calculation core, as a control target value of each of the actuators.