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    Semiconductor integrated circuit with memory redundancy circuit
    1.
    发明申请
    Semiconductor integrated circuit with memory redundancy circuit 有权

    公开(公告)号：US20070286001A1

    公开(公告)日：2007-12-13

    申请号：US11783123

    申请日：2007-04-06

    申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    IPC分类号： G11C7/00

    CPC分类号： G06F11/1008 ,  G11C29/848

    摘要： A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.

    Semiconductor integrated circuit with memory redundancy circuit
    2.
    发明授权
    Semiconductor integrated circuit with memory redundancy circuit 有权
    半导体集成电路与存储器冗余电路

    公开(公告)号：US07219272B2

    公开(公告)日：2007-05-15

    申请号：US10170583

    申请日：2002-06-14

    申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    IPC分类号： G11C29/00 ,  G06F11/00 ,  G11C7/00

    CPC分类号： G06F11/1008 ,  G11C29/848

    摘要： A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.

    摘要翻译： 一种具有存储器冗余电路的半导体集成电路，用于解决由使用ECC电路进行纠错引起的增加的面积，功耗和访问时间的问题。 该电路包括：多个存储垫; 平行于字线的本地总线，其传送读取数据并从存储器单元写入数据; 与数据线并行的写入全局总线，其从输入焊盘IO传送写入数据; 用于读取数据线的全局总线，其将读取的数据传送到输出焊盘IO; 以及位于全局总线和本地总线的交叉点处的至少一个纠错电路。 读取和写入可以在单个周期中完成，并且在写入操作期间，写入与先前读取的数据不同的数据。 通过这种配置，可以避免面积和功耗的增加，并且可以校正诸如软错误的错误。

    Semiconductor memory cells with shared p-type well
    3.
    发明授权
    Semiconductor memory cells with shared p-type well 有权
    具有共享p型的半导体存储器单元

    公开(公告)号：US07710764B2

    公开(公告)日：2010-05-04

    申请号：US11783123

    申请日：2007-04-06

    申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    IPC分类号： G11C11/00

    CPC分类号： G06F11/1008 ,  G11C29/848

    摘要： A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit includes: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.

    摘要翻译： 一种具有存储器冗余电路的半导体集成电路，用于解决由使用ECC电路进行纠错引起的增加的面积，功耗和访问时间的问题。 电路包括：多个存储垫; 平行于字线的本地总线，其传送读取数据并从存储器单元写入数据; 与数据线并行的写入全局总线，其从输入焊盘IO传送写入数据; 用于读取数据线的全局总线，其将读取的数据传送到输出焊盘IO; 以及位于全局总线和本地总线的交叉点处的至少一个纠错电路。 读取和写入可以在单个周期中完成，并且在写入操作期间，写入与先前读取的数据不同的数据。 通过这种配置，可以避免面积和功耗的增加，并且可以校正诸如软错误的错误。

    Semiconductor integrated circuit device
    4.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07737509B2

    公开(公告)日：2010-06-15

    申请号：US12216716

    申请日：2008-07-10

    申请人： Koichiro Ishibashi ,  Kenichi Osada

    发明人： Koichiro Ishibashi ,  Kenichi Osada

    IPC分类号： H01L27/088

    CPC分类号： G11C11/404 ,  G11C11/412 ,  G11C11/419 ,  G11C2207/104 ,  H01L21/823807 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1104 ,  Y10S257/903

    摘要： In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same substrate, the manufacturing process is complicated in order to set the circuits to the optimum values. As a result, in association with deterioration in the yield and increase in the number of manufacturing days, the manufacturing cost increases. In order to solve the problems, according to the invention, transistors of high and low thresholds are used in a logic circuit, a memory cell uses a transistor of the same high threshold voltage and a low threshold voltage transistor, and an input/output circuit uses a transistor having the same high threshold voltage and the same concentration in a channel, and a thicker gate oxide film.

    摘要翻译： 在集成电路器件中，根据电路的特性，存在各种最佳栅极长度，栅极氧化物膜的厚度和阈值电压。 在其中电路集成在同一基板上的半导体集成电路器件中，制造过程复杂以便将电路设置为最佳值。 结果，伴随着产量的恶化和制造日数的增加，制造成本增加。 为了解决这些问题，根据本发明，在逻辑电路中使用高阈值和低阈值的晶体管，存储单元使用具有相同高阈值电压的晶体管和低阈值电压晶体管，以及输入/输出电路 使用在通道中具有相同高阈值电压和相同浓度的晶体管，以及较厚的栅极氧化物膜。

    Semiconductor memory device with memory cells operated by boosted voltage
    5.
    发明申请
    Semiconductor memory device with memory cells operated by boosted voltage 有权
    具有由升压电压工作的存储单元的半导体存储器件

    公开(公告)号：US20070133260A1

    公开(公告)日：2007-06-14

    申请号：US11657026

    申请日：2007-01-24

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    IPC分类号： G11C11/00

    CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

    摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

    摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOS晶体管的电导被增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。 此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。

    Semiconductor integrated circuit device
    9.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20050146961A1

    公开(公告)日：2005-07-07

    申请号：US11042172

    申请日：2005-01-26

    申请人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    发明人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC分类号： H01L27/10 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/02

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    摘要： Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

    摘要翻译： 现有的已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底进行电接触，这将导致 不对称性导致了微图案化困难的问题的发生。 为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分为两部分，它们设置在N型阱区NW 1的相对侧，并形成为 形成晶体管的扩散层没有曲率，同时使得布局方向在平行于边界线和位线的方向上运行。 在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。

    Semiconductor memory device with memory cells operated by boosted voltage
    10.
    发明授权
    Semiconductor memory device with memory cells operated by boosted voltage 有权
    具有由升压电压工作的存储单元的半导体存储器件

    公开(公告)号：US06795332B2

    公开(公告)日：2004-09-21

    申请号：US10163310

    申请日：2002-06-07

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    IPC分类号： G11C1100

    CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

    摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOB transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOB transistors is in-creased, the threshold voltage of the MOB transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOB transistor can be set to 1, thereby allowing a reduction in the memory cell area.

    摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOB晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOB晶体管的电导被增加，所以可以减小存储单元内的MOB晶体管的阈值电压，而不会降低静态噪声容限。 此外，可以将驱动器MOS晶体管和转移MOB晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。