公开(公告)号：US07595259B2

公开(公告)日：2009-09-29

申请号：US11597711

申请日：2005-05-27

申请人： Kenji Kohiro ,  Kazumasa Ueda ,  Masahiko Hata

发明人： Kenji Kohiro ,  Kazumasa Ueda ,  Masahiko Hata

IPC分类号： H01L21/4763

CPC分类号： H01L29/861 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02661 ,  H01L29/66136

摘要： A compound semiconductor substrate manufacturing method suitable for manufacturing a compound semiconductor element having high electrical characteristics. The compound semiconductor substrate manufacturing method is a method for manufacturing a compound semiconductor substrate having pn junction, including an epitaxial growing process, a selective growing process and other discretionary processes after the epitaxial growing process. The highest temperatures in the selective growing process and other discretionary processes after the epitaxial growing process are lower than that in the epitaxial growing process prior to the selective growing process.

摘要翻译： 一种适用于制造具有高电特性的化合物半导体元件的化合物半导体衬底制造方法。 化合物半导体衬底制造方法是在外延生长工艺之后制造具有pn结的化合物半导体衬底的方法，包括外延生长工艺，选择性生长工艺和其它任意处理。 选择性生长过程中的最高温度和外延生长过程之后的其他任意处理比在选择性生长过程之前的外延生长过程中的温度低。

公开(公告)号：US20070232018A1

公开(公告)日：2007-10-04

申请号：US11597711

申请日：2005-05-27

申请人： Kenji Kohiro ,  Kazumasa Ueda ,  Masahiko Hata

发明人： Kenji Kohiro ,  Kazumasa Ueda ,  Masahiko Hata

IPC分类号： H01L21/20

CPC分类号： H01L29/861 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02661 ,  H01L29/66136

摘要： A compound semiconductor substrate manufacturing method suitable for manufacturing a compound semiconductor element having high electrical characteristics. The compound semiconductor substrate manufacturing method is a method for manufacturing a compound semiconductor substrate having pn junction, including an epitaxial growing process, a selective growing process and other discretionary processes after the epitaxial growing process. The highest temperatures in the selective growing process and other discretionary processes after the epitaxial growing process are lower than that in the epitaxial growing process prior to the selective growing process.

摘要翻译： 一种适用于制造具有高电特性的化合物半导体元件的化合物半导体衬底制造方法。 化合物半导体衬底制造方法是在外延生长工艺之后制造具有pn结的化合物半导体衬底的方法，包括外延生长工艺，选择性生长工艺和其它任意处理。 选择性生长过程中的最高温度和外延生长过程之后的其他任意处理比在选择性生长过程之前的外延生长过程中的温度低。

公开(公告)号：US20070158684A1

公开(公告)日：2007-07-12

申请号：US10560160

申请日：2004-05-24

申请人： Kenji Kohiro ,  Kazumasa Ueda ,  Toshimitsu Abe ,  Masahiko Hata

发明人： Kenji Kohiro ,  Kazumasa Ueda ,  Toshimitsu Abe ,  Masahiko Hata

IPC分类号： H01L31/00

CPC分类号： H01L29/7783 ,  H01L21/02395 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/0262

摘要： An InGaP buffer layer (3) is formed on a semi-insulating GaAs substrate (1) to a thickness of not less than 5 nm and not greater than 500 nm and an InAlAs layer (4) and an InGaAs channel layer (5) are grown thereon to form a heterostructure. An In segregation effect occurs at the time of forming the InGaP buffer layer (3), so that the region of the InGaP buffer layer (3) near the layer above becomes excessive in In. As a result, the composition of the surface of the InGaP buffer layer (3) becomes very close to the composition of InP, thereby suppressing occurrence of misfit dislocations that can result in degradation of the surface condition. Further, the surface condition of the InAlAs layer (4) and InGaAs channel layer (5) formed thereon can be made good.

摘要翻译： 在半绝缘GaAs衬底（1）上形成厚度不小于5nm且不大于500nm的InGaP缓冲层（3），并且InAlAs层（4）和InGaAs沟道层（5）为 在其上生长以形成异质结构。 在形成InGaP缓冲层（3）时发生An偏析效应，使得In附近的InGaP缓冲层（3）的区域变得过大。 结果，InGaP缓冲层（3）的表面的组成变得非常接近InP的组成，从而抑制可能导致表面状态劣化的失配位错的发生。 此外，可以使形成在其上的InAlAs层（4）和InGaAs沟道层（5）的表面状态良好。

公开(公告)号：US20070215905A1

公开(公告)日：2007-09-20

申请号：US11597613

申请日：2005-05-26

申请人： Kenji Kohiro ,  Tomoyuki Takada ,  Kazumasa Ueda ,  Masahiko Hata

发明人： Kenji Kohiro ,  Tomoyuki Takada ,  Kazumasa Ueda ,  Masahiko Hata

IPC分类号： H01L21/20

CPC分类号： H01L29/7785 ,  H01L21/0237 ,  H01L21/02395 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/0262

摘要： A compound semiconductor epitaxial substrate and a process for producing the same are provided. The compound semiconductor epitaxial substrate comprises a single crystal substrate, a lattice mismatch compound semiconductor layer and a stress compensation layer, wherein the lattice mismatch compound semiconductor layer and the stress compensation layer are disposed on the identical surface side of the single crystal substrate, there is no occurrence of lattice relaxation in the lattice mismatch compound semiconductor layer, as well as the stress compensation layer, and Ls representing the lattice constant of the single crystal substrate, Lm representing the lattice constant of the lattice mismatch compound semiconductor layer, and Lc representing the lattice constant of the stress compensation layer satisfy the formula (1a) or (1b). Lm Ls>Lc  (2a)

摘要翻译： 提供了一种化合物半导体外延基板及其制造方法。 化合物半导体外延基板包括单晶衬底，晶格失配化合物半导体层和应力补偿层，其中晶格失配化合物半导体层和应力补偿层设置在单晶衬底的相同表面侧上，存在 在晶格失配化合物半导体层以及应力补偿层中不发生晶格弛豫，表示单晶衬底的晶格常数的Ls表示晶格失配化合物半导体层的晶格常数，Lm表示 应力补偿层的晶格常数满足公式（1a）或（1b）。 <？in-line-formula description =“In-line Formulas”end =“lead”？> Lm <？in-line-formula description =“In-line Formulas”end =“lead”？> Lm> Ls> Lc（2a）<？in-line-formula description =“In-line Formulas”end = 尾巴“？>

公开(公告)号：US08906158B2

公开(公告)日：2014-12-09

申请号：US11660936

申请日：2005-08-23

申请人： Kenji Kohiro ,  Kazumasa Ueda ,  Masahiko Hata

发明人： Kenji Kohiro ,  Kazumasa Ueda ,  Masahiko Hata

IPC分类号： H01L29/861 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/861 ,  H01L21/02395 ,  H01L21/02546 ,  H01L21/02579 ,  H01L21/02639 ,  H01L29/66136

摘要： Disclosed is a method for producing a compound semiconductor epitaxial substrate having a pn junction by selective growth which is characterized by using a base substrate having an average residual strain of not more than 1.0×10−5.

摘要翻译： 公开了一种通过选择性生长制备具有pn结的化合物半导体外延基板的方法，其特征在于使用平均残余应变不大于1.0×10-5的基底。

公开(公告)号：US08169004B2

公开(公告)日：2012-05-01

申请号：US11597613

申请日：2005-05-26

申请人： Kenji Kohiro ,  Tomoyuki Takada ,  Kazumasa Ueda ,  Masahiko Hata

发明人： Kenji Kohiro ,  Tomoyuki Takada ,  Kazumasa Ueda ,  Masahiko Hata

IPC分类号： H01L21/20

CPC分类号： H01L29/7785 ,  H01L21/0237 ,  H01L21/02395 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/0262

摘要： A compound semiconductor epitaxial substrate and a process for producing the same are provided. The compound semiconductor epitaxial substrate comprises a single crystal substrate, a lattice mismatch compound semiconductor layer and a stress compensation layer, wherein the lattice mismatch compound semiconductor layer and the stress compensation layer are disposed on the identical surface side of the single crystal substrate, there is no occurrence of lattice relaxation in the lattice mismatch compound semiconductor layer, as well as the stress compensation layer, and Ls representing the lattice constant of the single crystal substrate, Lm representing the lattice constant of the lattice mismatch compound semiconductor layer, and Lc representing the lattice constant of the stress compensation layer satisfy the formula (1a) or (1b). Lm Lm>Ls>Lc  (2a)

摘要翻译： 提供了一种化合物半导体外延基板及其制造方法。 化合物半导体外延基板包括单晶衬底，晶格失配化合物半导体层和应力补偿层，其中晶格失配化合物半导体层和应力补偿层设置在单晶衬底的相同表面侧上，存在 在晶格失配化合物半导体层以及应力补偿层中不发生晶格弛豫，表示单晶衬底的晶格常数的Ls表示晶格失配化合物半导体层的晶格常数，Lm表示 应力补偿层的晶格常数满足式（1a）或（1b）。 Lm Lm> Ls> Lc（2a）

公开(公告)号：US20090031944A1

公开(公告)日：2009-02-05

申请号：US11660936

申请日：2005-08-23

申请人： Kenji Kohiro ,  Kazumasa Ueda ,  Masahiko Hata

发明人： Kenji Kohiro ,  Kazumasa Ueda ,  Masahiko Hata

IPC分类号： C30B11/00

CPC分类号： H01L29/861 ,  H01L21/02395 ,  H01L21/02546 ,  H01L21/02579 ,  H01L21/02639 ,  H01L29/66136

摘要： Disclosed is a method for producing a compound semiconductor epitaxial substrate having a pn junction by selective growth which is characterized by using a base substrate having an average residual strain of not more than 1.0×10−5.

摘要翻译： 公开了一种通过选择性生长制备具有pn结的化合物半导体外延基板的方法，其特征在于使用平均残余应变不大于1.0×10 -5的基底。

公开(公告)号：US20070082467A1

公开(公告)日：2007-04-12

申请号：US10577069

申请日：2004-10-25

申请人： Masahiko Hata ,  Yoshinobu Ono ,  Kazumasa Ueda

发明人： Masahiko Hata ,  Yoshinobu Ono ,  Kazumasa Ueda

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L31/20 ,  H01L21/30 ,  H01L21/46

CPC分类号： H01L29/66462 ,  H01L21/2007 ,  H01L29/2003

摘要： The present invention provides a method for manufacturing a compound semiconductor substrate. The method for manufacturing a compound semiconductor substrate comprises the steps of: (a) epitaxially growing a compound semiconductor functional layer 2 on a substrate 1, (b) bonding a support substrate 3 to the compound semiconductor functional layer 2, (c) polishing the substrate 1 and a part of the compound semiconductor functional layer 2 on the side which is in contact with the substrate 1, to remove them, (d) bonding a thermally conductive substrate 4 having a thermal conductivity higher than that of the substrate 1 to the exposed surface of the compound semiconductor functional layer 2 which is provided in the step (c) to obtain a multilayer substrate and (d) separating the support substrate 3 from the multilayer substrate.

摘要翻译： 本发明提供一种化合物半导体衬底的制造方法。 制造化合物半导体衬底的方法包括以下步骤：（a）在衬底1上外延生长化合物半导体功能层2，（b）将支撑衬底3接合到化合物半导体功能层2，（c） 基板1和与基板1接触的一侧的化合物半导体功能层2的一部分，以除去它们;（d）将具有比基板1的导热率高的导热性基板4接合到 在步骤（c）中提供的化合物半导体功能层2的暴露表面以获得多层基板，以及（d）将支撑基板3与多层基板分离。

公开(公告)号：US07811839B2

公开(公告)日：2010-10-12

申请号：US11883805

申请日：2006-02-16

申请人： Kenji Kasahara ,  Kazumasa Ueda

发明人： Kenji Kasahara ,  Kazumasa Ueda

IPC分类号： H01L21/00 ,  H01L29/18

CPC分类号： H01L21/30621 ,  H01L33/08

摘要： The present invention provides a semiconductor light emitting device and a method for manufacturing the same. The semiconductor device comprises (i) a semiconductor layer with convex portions in a shape selected from a cone and a truncated cone and (ii) electrodes, wherein in the case of the convex portions with the shape of the truncated cone, the convex portions has a height of from 0.05 to 5.0 μm and a bottom base diameter of from 0.05 to 2.0 μm; in case of the convex portions with the shape of the cone, the convex portions has a height of from 0.05 to 5.0 μm and a base diameter of from 0.05 to 2.0 μm. A method for manufacturing a semiconductor light emitting device comprising the steps of (a) growing a semiconductor layer on a substrate, (b) forming on the semiconductor layer a region having particles with an average particle diameter of 0.01 to 10 μm and a surface density of 2×106 to 2×1010 cm−2, and (c) dry-etching the semiconductor layer to form convex portions in the shape selected from a cone and a truncated corn.

摘要翻译： 本发明提供一种半导体发光器件及其制造方法。 半导体器件包括（i）具有选自锥体和截头圆锥形状的凸部的半导体层和（ii）电极，其中在具有截头圆锥形状的凸部的情况下，凸部具有 高度为0.05〜5.0μm，底底直径为0.05〜2.0μm; 在具有锥形形状的凸部的情况下，凸部的高度为0.05〜5.0μm，基径为0.05〜2.0μm。 一种制造半导体发光器件的方法，包括以下步骤：（a）在衬底上生长半导体层，（b）在半导体层上形成具有平均粒径为0.01至10μm的颗粒的区域和表面密度 为2×10 6〜2×10 10 cm -2，（c）对半导体层进行干法蚀刻，形成选自圆锥体和截玉米的形状的凸部。

公开(公告)号：US08097887B2

公开(公告)日：2012-01-17

申请号：US12225697

申请日：2007-03-27

申请人： Sadanori Yamanaka ,  Yoshinobu Ono ,  Kazumasa Ueda

发明人： Sadanori Yamanaka ,  Yoshinobu Ono ,  Kazumasa Ueda

IPC分类号： H01L27/15 ,  H01L29/26 ,  H01L31/12 ,  H01L33/00 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/22

CPC分类号： H01L33/22 ,  H01L33/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a light emitting device. The light emitting device has a light distribution in which a light distribution I (θ, φ) obtained when light emitted from a chip of the light emitting device is directly measured is not dependent on a direction φ and is substantially represented by I (θ, φ)=I (θ). I (θ, φ) represents a light intensity distribution in a direction (θ, φ), θ represents an angle from a direction of a normal to a light extraction surface of the light emitting device (0≦θ≦90°), φ represents a rotation angle around the normal (0≦φ≦360°), and I (θ) represents a monotone decreasing function with which 0 is approached when θ=90° is satisfied. In the light emitting device, of a structural body constructing the chip of the light emitting device, with regard to a size of a portion of the structural body which is transparent to light emitted from a light emitting layer, a ratio (an aspect ratio) between the size in a lateral direction and the size in a thickness direction is not less than 5 and a structure having a light scattering function is provided on a surface of the light emitting device chip or in an interior of the transparent portion of the structural body.

摘要翻译： 本发明提供一种发光装置。 发光装置具有光分布，其中直接测量从发光器件的芯片发出的光所获得的光分布I（＆amp;θ; ph ph）不依赖于方向＆phgr; 并且基本上由I（＆Thetas;＆phgr;）= I（＆thetas;）表示。 I（＆thetas;＆phgr。）表示方向（＆thetas;＆phgr;），＆thetas的光强度分布; 表示从发光器件的法线方向到光提取表面的角度（0＆amp; nlE;＆hell;＆nlE; 90°），＆phgr; 表示正常（0＆nlE;＆phgr;＆nlE; 360°）周围的旋转角度，I（＆Thetas;）表示满足＆amp; t = 90°的单调递减函数，接近0。 在构成发光装置的芯片的结构体的发光装置中，对于从发光层发出的光透明的结构体的一部分的尺寸，比率（纵横比） 在横向尺寸和厚度方向之间的尺寸不小于5，并且在发光元件芯片的表面上或在结构体的透明部分的内部设置具有光散射功能的结构 。