公开(公告)号：US07595259B2

公开(公告)日：2009-09-29

申请号：US11597711

申请日：2005-05-27

申请人： Kenji Kohiro ,  Kazumasa Ueda ,  Masahiko Hata

发明人： Kenji Kohiro ,  Kazumasa Ueda ,  Masahiko Hata

IPC分类号： H01L21/4763

CPC分类号： H01L29/861 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02661 ,  H01L29/66136

摘要： A compound semiconductor substrate manufacturing method suitable for manufacturing a compound semiconductor element having high electrical characteristics. The compound semiconductor substrate manufacturing method is a method for manufacturing a compound semiconductor substrate having pn junction, including an epitaxial growing process, a selective growing process and other discretionary processes after the epitaxial growing process. The highest temperatures in the selective growing process and other discretionary processes after the epitaxial growing process are lower than that in the epitaxial growing process prior to the selective growing process.

摘要翻译： 一种适用于制造具有高电特性的化合物半导体元件的化合物半导体衬底制造方法。 化合物半导体衬底制造方法是在外延生长工艺之后制造具有pn结的化合物半导体衬底的方法，包括外延生长工艺，选择性生长工艺和其它任意处理。 选择性生长过程中的最高温度和外延生长过程之后的其他任意处理比在选择性生长过程之前的外延生长过程中的温度低。

公开(公告)号：US20070232018A1

公开(公告)日：2007-10-04

申请号：US11597711

申请日：2005-05-27

申请人： Kenji Kohiro ,  Kazumasa Ueda ,  Masahiko Hata

发明人： Kenji Kohiro ,  Kazumasa Ueda ,  Masahiko Hata

IPC分类号： H01L21/20

CPC分类号： H01L29/861 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02661 ,  H01L29/66136

摘要： A compound semiconductor substrate manufacturing method suitable for manufacturing a compound semiconductor element having high electrical characteristics. The compound semiconductor substrate manufacturing method is a method for manufacturing a compound semiconductor substrate having pn junction, including an epitaxial growing process, a selective growing process and other discretionary processes after the epitaxial growing process. The highest temperatures in the selective growing process and other discretionary processes after the epitaxial growing process are lower than that in the epitaxial growing process prior to the selective growing process.

摘要翻译： 一种适用于制造具有高电特性的化合物半导体元件的化合物半导体衬底制造方法。 化合物半导体衬底制造方法是在外延生长工艺之后制造具有pn结的化合物半导体衬底的方法，包括外延生长工艺，选择性生长工艺和其它任意处理。 选择性生长过程中的最高温度和外延生长过程之后的其他任意处理比在选择性生长过程之前的外延生长过程中的温度低。

公开(公告)号：US20070158684A1

公开(公告)日：2007-07-12

申请号：US10560160

申请日：2004-05-24

申请人： Kenji Kohiro ,  Kazumasa Ueda ,  Toshimitsu Abe ,  Masahiko Hata

发明人： Kenji Kohiro ,  Kazumasa Ueda ,  Toshimitsu Abe ,  Masahiko Hata

IPC分类号： H01L31/00

CPC分类号： H01L29/7783 ,  H01L21/02395 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/0262

摘要： An InGaP buffer layer (3) is formed on a semi-insulating GaAs substrate (1) to a thickness of not less than 5 nm and not greater than 500 nm and an InAlAs layer (4) and an InGaAs channel layer (5) are grown thereon to form a heterostructure. An In segregation effect occurs at the time of forming the InGaP buffer layer (3), so that the region of the InGaP buffer layer (3) near the layer above becomes excessive in In. As a result, the composition of the surface of the InGaP buffer layer (3) becomes very close to the composition of InP, thereby suppressing occurrence of misfit dislocations that can result in degradation of the surface condition. Further, the surface condition of the InAlAs layer (4) and InGaAs channel layer (5) formed thereon can be made good.

摘要翻译： 在半绝缘GaAs衬底（1）上形成厚度不小于5nm且不大于500nm的InGaP缓冲层（3），并且InAlAs层（4）和InGaAs沟道层（5）为 在其上生长以形成异质结构。 在形成InGaP缓冲层（3）时发生An偏析效应，使得In附近的InGaP缓冲层（3）的区域变得过大。 结果，InGaP缓冲层（3）的表面的组成变得非常接近InP的组成，从而抑制可能导致表面状态劣化的失配位错的发生。 此外，可以使形成在其上的InAlAs层（4）和InGaAs沟道层（5）的表面状态良好。

公开(公告)号：US08169004B2

公开(公告)日：2012-05-01

申请号：US11597613

申请日：2005-05-26

申请人： Kenji Kohiro ,  Tomoyuki Takada ,  Kazumasa Ueda ,  Masahiko Hata

发明人： Kenji Kohiro ,  Tomoyuki Takada ,  Kazumasa Ueda ,  Masahiko Hata

IPC分类号： H01L21/20

CPC分类号： H01L29/7785 ,  H01L21/0237 ,  H01L21/02395 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/0262

摘要： A compound semiconductor epitaxial substrate and a process for producing the same are provided. The compound semiconductor epitaxial substrate comprises a single crystal substrate, a lattice mismatch compound semiconductor layer and a stress compensation layer, wherein the lattice mismatch compound semiconductor layer and the stress compensation layer are disposed on the identical surface side of the single crystal substrate, there is no occurrence of lattice relaxation in the lattice mismatch compound semiconductor layer, as well as the stress compensation layer, and Ls representing the lattice constant of the single crystal substrate, Lm representing the lattice constant of the lattice mismatch compound semiconductor layer, and Lc representing the lattice constant of the stress compensation layer satisfy the formula (1a) or (1b). Lm Lm>Ls>Lc  (2a)

摘要翻译： 提供了一种化合物半导体外延基板及其制造方法。 化合物半导体外延基板包括单晶衬底，晶格失配化合物半导体层和应力补偿层，其中晶格失配化合物半导体层和应力补偿层设置在单晶衬底的相同表面侧上，存在 在晶格失配化合物半导体层以及应力补偿层中不发生晶格弛豫，表示单晶衬底的晶格常数的Ls表示晶格失配化合物半导体层的晶格常数，Lm表示 应力补偿层的晶格常数满足式（1a）或（1b）。 Lm Lm> Ls> Lc（2a）

公开(公告)号：US20090031944A1

公开(公告)日：2009-02-05

申请号：US11660936

申请日：2005-08-23

申请人： Kenji Kohiro ,  Kazumasa Ueda ,  Masahiko Hata

发明人： Kenji Kohiro ,  Kazumasa Ueda ,  Masahiko Hata

IPC分类号： C30B11/00

CPC分类号： H01L29/861 ,  H01L21/02395 ,  H01L21/02546 ,  H01L21/02579 ,  H01L21/02639 ,  H01L29/66136

摘要： Disclosed is a method for producing a compound semiconductor epitaxial substrate having a pn junction by selective growth which is characterized by using a base substrate having an average residual strain of not more than 1.0×10−5.

摘要翻译： 公开了一种通过选择性生长制备具有pn结的化合物半导体外延基板的方法，其特征在于使用平均残余应变不大于1.0×10 -5的基底。

公开(公告)号：US08906158B2

公开(公告)日：2014-12-09

申请号：US11660936

申请日：2005-08-23

申请人： Kenji Kohiro ,  Kazumasa Ueda ,  Masahiko Hata

发明人： Kenji Kohiro ,  Kazumasa Ueda ,  Masahiko Hata

IPC分类号： H01L29/861 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/861 ,  H01L21/02395 ,  H01L21/02546 ,  H01L21/02579 ,  H01L21/02639 ,  H01L29/66136

摘要： Disclosed is a method for producing a compound semiconductor epitaxial substrate having a pn junction by selective growth which is characterized by using a base substrate having an average residual strain of not more than 1.0×10−5.

摘要翻译： 公开了一种通过选择性生长制备具有pn结的化合物半导体外延基板的方法，其特征在于使用平均残余应变不大于1.0×10-5的基底。

公开(公告)号：US20070215905A1

公开(公告)日：2007-09-20

申请号：US11597613

申请日：2005-05-26

申请人： Kenji Kohiro ,  Tomoyuki Takada ,  Kazumasa Ueda ,  Masahiko Hata

发明人： Kenji Kohiro ,  Tomoyuki Takada ,  Kazumasa Ueda ,  Masahiko Hata

IPC分类号： H01L21/20

CPC分类号： H01L29/7785 ,  H01L21/0237 ,  H01L21/02395 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/0262

摘要： A compound semiconductor epitaxial substrate and a process for producing the same are provided. The compound semiconductor epitaxial substrate comprises a single crystal substrate, a lattice mismatch compound semiconductor layer and a stress compensation layer, wherein the lattice mismatch compound semiconductor layer and the stress compensation layer are disposed on the identical surface side of the single crystal substrate, there is no occurrence of lattice relaxation in the lattice mismatch compound semiconductor layer, as well as the stress compensation layer, and Ls representing the lattice constant of the single crystal substrate, Lm representing the lattice constant of the lattice mismatch compound semiconductor layer, and Lc representing the lattice constant of the stress compensation layer satisfy the formula (1a) or (1b). Lm Ls>Lc  (2a)

摘要翻译： 提供了一种化合物半导体外延基板及其制造方法。 化合物半导体外延基板包括单晶衬底，晶格失配化合物半导体层和应力补偿层，其中晶格失配化合物半导体层和应力补偿层设置在单晶衬底的相同表面侧上，存在 在晶格失配化合物半导体层以及应力补偿层中不发生晶格弛豫，表示单晶衬底的晶格常数的Ls表示晶格失配化合物半导体层的晶格常数，Lm表示 应力补偿层的晶格常数满足公式（1a）或（1b）。 <？in-line-formula description =“In-line Formulas”end =“lead”？> Lm <？in-line-formula description =“In-line Formulas”end =“lead”？> Lm> Ls> Lc（2a）<？in-line-formula description =“In-line Formulas”end = 尾巴“？>

公开(公告)号：US08492750B2

公开(公告)日：2013-07-23

申请号：US12935379

申请日：2009-03-24

申请人： Kenji Kohiro ,  Shinichi Yamate ,  Akiko Nakazono

发明人： Kenji Kohiro ,  Shinichi Yamate ,  Akiko Nakazono

IPC分类号： H01L35/24

CPC分类号： H01L51/0054 ,  H01L51/0036 ,  H01L51/0039 ,  H01L51/0043 ,  H01L51/0055 ,  H01L51/0074 ,  H01L51/0094 ,  H01L51/0512 ,  H01L51/0558

摘要： An object of the present invention is to provide an organic semiconductor composition capable of forming an organic film having high carrier transportability. A preferable organic semiconductor composition contains a lower molecular weight compound and a higher molecular weight compound having carrier transportability, and the solubility parameter of the higher molecular weight compound and the solubility parameter of the lower molecular weight compound differ by 0.6 to 1.5.

摘要翻译： 本发明的目的是提供一种能形成具有高载流子传输性的有机膜的有机半导体组合物。 优选的有机半导体组合物含有较低分子量化合物和具有载体迁移性的较高分子量化合物，较高分子量化合物的溶解度参数和较低分子量化合物的溶解度参数相差0.6至1.5。

公开(公告)号：US5454346A

公开(公告)日：1995-10-03

申请号：US194507

申请日：1994-02-10

申请人： Masayuki Uchida ,  Kenji Kohiro ,  Osamu Oda

发明人： Masayuki Uchida ,  Kenji Kohiro ,  Osamu Oda

IPC分类号： C30B11/06 ,  C30B11/00 ,  C30B27/00 ,  H01L21/208 ,  C30B11/08

CPC分类号： C30B29/40 ,  C30B11/00 ,  Y10T117/1092

摘要： A process for growing a multielement compound single crystal, includes the steps of placing a crucible holding a raw multielement compound of a predetermined set of composition ratios Y in a vertical crystal growing furnace having a heater, melting the raw multielement compound held in the crucible with the heater to produce a melt of the raw multielement compound in the crucible, controlling the output of the heater to grow a multielement compound single crystal of a predetermined set of composition ratios X from the melt so that the melt is solidified successively upwards from part of the melt in contact with the bottom of the crucible, and feeding to the melt as a solute at least one element of the raw multielement compound from above the level of the melt in the crucible so as to maintain the predetermined set of composition ratios X of the solute during growth of the multielement compound single crystal. The process can keep constant the composition of the grown multielement compound single crystal. The process is applicable to the growth of multielement compound semiconductor single crystals and multielement compound oxide single crystals.

摘要翻译： 用于生长多元素化合物单晶的方法包括以下步骤：将具有预定组成比Y的原料多元素化合物的坩埚放置在具有加热器的垂直晶体生长炉中，将保持在坩埚中的原料多元素化合物熔化， 加热器，以在坩埚中产生原料多元素化合物的熔体，控制加热器的输出以从熔体中生长具有预定组成比X的组合的多元素化合物单晶，使得熔体从部分 所述熔体与所述坩埚的底部接触，并且从所述坩埚中的所述熔体的高度上方以至少一种元素的原料多元素化合物作为溶质供给到所述熔体中，以保持所述熔融物的组成比X的预定组合 多元素化合物单晶生长过程中的溶质。 该方法可以使生长的多元素化合物单晶的组成保持恒定。 该方法适用于多元素化合物半导体单晶和多元素复合氧化物单晶的生长。

公开(公告)号：US09178165B2

公开(公告)日：2015-11-03

申请号：US13809705

申请日：2011-07-13

申请人： Kenji Kohiro ,  Takayuki Okachi

发明人： Kenji Kohiro ,  Takayuki Okachi

IPC分类号： H01L51/00 ,  H01L51/05

CPC分类号： H01L51/0071 ,  C09B57/00 ,  C09B57/008 ,  C09B69/109 ,  H01L51/0036 ,  H01L51/0039 ,  H01L51/0074 ,  H01L51/0558

摘要： To provide an organic semiconductor composition that can exhibit a high carrier transport property and give uniform characteristics. An organic semiconductor composition characterized by containing a high molecular weight compound having a carrier transport property and a low molecular weight compound, in which the low molecular weight compound has a structure represented by Formula (1) and a content ratio of the low molecular weight compound is from 5 to 95 parts by mass relative to a total of 100 parts by mass of the high molecular weight compound and the low molecular weight compound, [where, E represents a sulfur atom or a selenium atom, three E's may be the same or may be different from one another, and an aromatic ring in Formula may have substituents].

摘要翻译： 提供能够表现出高载流子传输性并赋予均匀特性的有机半导体组合物。 一种有机半导体组合物，其特征在于含有具有载流子传输性的高分子量化合物和低分子量化合物，其中低分子量化合物具有由式（1）表示的结构和低分子量化合物 相对于总共100质量份的高分子量化合物和低分子量化合物为5〜95质量份[其中，E表示硫原子或硒原子，3个E可以相同或相同， 可以彼此不同，并且式中的芳环可以具有取代基]。