利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

31 条记录 (耗时 0.025 秒)

    Self regulating temperature/performance/voltage scheme for micros (X86)
    3.
    发明授权
    Self regulating temperature/performance/voltage scheme for micros (X86) 有权
    微调自适应温度/性能/电压方案（X86）

    公开(公告)号：US6119241A

    公开(公告)日：2000-09-12

    申请号：US183342

    申请日：1998-10-30

    申请人： Michel Salib Michail ,  Wilbur David Pricer ,  Sebastian Theodore Ventrone

    发明人： Michel Salib Michail ,  Wilbur David Pricer ,  Sebastian Theodore Ventrone

    IPC分类号： G06F1/08 ,  G06F1/20 ,  G06F1/32 ,  G06F1/26

    CPC分类号： G06F1/324 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3296 ,  Y02B60/1217 ,  Y02B60/1285

    摘要： A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.

    摘要翻译： 一种处理器，通过使用包括电压，时钟和由处理器或其系统执行的操作的变量的层次来机会地优化性能。 本发明通过定义各种状态来实现性能优化，目的在于处理器执行单元正在运行时处理器处于加速电压和时钟的最佳性能状态。 状态由逻辑网络基于由温度传感器和性能控制提供的信息来选择。 逻辑网络可以设想为一个UP-DOWN计数器。 根据条件，计数器可以向上或向下进入状态“梯子”。

    Anticipating cache memory loader and method
    5.
    发明授权
    Anticipating cache memory loader and method 失效
    预测缓存内存加载器和方法

    公开(公告)号：US6026471A

    公开(公告)日：2000-02-15

    申请号：US751468

    申请日：1996-11-19

    申请人： Kenneth Joseph Goodnow ,  Clarence Rosser Ogilvie ,  Wilbur David Pricer ,  Sebastian Theodore Ventrone

    发明人： Kenneth Joseph Goodnow ,  Clarence Rosser Ogilvie ,  Wilbur David Pricer ,  Sebastian Theodore Ventrone

    IPC分类号： G06F9/46 ,  G06F12/08 ,  G06F12/10 ,  G06F17/12

    CPC分类号： G06F12/0862 ,  G06F9/461 ,  G06F2212/6024

    摘要： According to the present invention, an anticipating cache memory loader is provided to "pre-load" the cache with the data and instructions most likely to be needed by the CPU once the currently executing task is completed or interrupted. The data and instructions most likely to be needed after the currently executing task is completed or executed is the same data and instructions that were loaded into the cache at the time the next scheduled task was last preempted or interrupted. By creating and storing an index to the contents of the cache for various tasks at the point in time the tasks are interrupted, the data and instructions previously swapped out of the cache can be retrieved from main memory and restored to the cache when needed. By using available bandwidth to pre-load the cache for the next scheduled task, the CPU can begin processing the next scheduled task more quickly and efficiently than if the present invention were not utilized. Using the present invention, CPU stalls will be reduced because the CPU will operate more efficiently without waiting for excessive periods of time for the cache to be loaded with relevant data and instructions.

    摘要翻译： 根据本发明，提供一种预期的高速缓存存储器加载器，用于在当前执行的任务完成或中断之后，用CPU最有可能需要的数据和指令来“预加载”高速缓存。 在完成或执行当前执行任务之后最可能需要的数据和指令是在下一个计划任务最后被抢占或中断时加载到缓存中的相同数据和指令。 通过在任务中断的时间点为各种任务创建和存储索引到高速缓存的内容，可以从主存储器中检索先前从高速缓存交换的数据和指令，并在需要时将其还原到高速缓存。 通过使用可用带宽来预加载用于下一个计划任务的高速缓存，与不利用本发明相比，CPU可以更快速和有效地开始处理下一个计划的任务。 使用本发明，CPU停止将被减少，因为CPU将更有效地操作而不用等待超时间段来缓存相关数据和指令。

    Internal shadow latch
    6.
    发明授权
    Internal shadow latch 失效
    内部阴影闩锁

    公开(公告)号：US5986962A

    公开(公告)日：1999-11-16

    申请号：US121232

    申请日：1998-07-23

    申请人： Claude L Bertin ,  Kenneth Joseph Goodnow ,  Wilbur David pricer ,  Sebastian Theodore Ventrone

    发明人： Claude L Bertin ,  Kenneth Joseph Goodnow ,  Wilbur David pricer ,  Sebastian Theodore Ventrone

    IPC分类号： G11C11/413 ,  G11C14/00 ,  G11C11/40

    CPC分类号： G11C14/00 ,  G11C11/413

    摘要： An integrated circuit implements simple and efficient normal power to low power and low power to normal power transitions. Dedicated shadow latch circuits are added, each having a corresponding system latch. The state of the system latches is transferred to the shadow latches upon a transition from normal to low power mode and the stored information is transferred back to the system latches on the transition from low power to normal power operation. The shadow latches are optimized to minimize power usage during low power operation.

    摘要翻译： 集成电路实现简单而有效的正常功率到低功率和低功率到正常功率转换。 添加专用的阴影锁存电路，每个都具有相应的系统锁存器。 系统锁存器的状态在从正常模式转换到低功耗模式时被传送到阴影锁存器，并且存储的信息从低功耗转换到正常工作状态转换回系统锁存器。 阴影锁存器被优化以在低功率操作期间最小化功率使用。

    Apparatus and method for prefetching data based on information contained in a compiler generated program map
    7.
    发明授权
    Apparatus and method for prefetching data based on information contained in a compiler generated program map 失效
    基于编译器生成的程序映射中包含的信息来预取数据的装置和方法

    公开(公告)号：US5918246A

    公开(公告)日：1999-06-29

    申请号：US788870

    申请日：1997-01-23

    申请人： Kenneth Joseph Goodnow ,  Clarence Rosser Ogilvie ,  Wilbur David Pricer ,  Sebastian Theodore Ventrone

    发明人： Kenneth Joseph Goodnow ,  Clarence Rosser Ogilvie ,  Wilbur David Pricer ,  Sebastian Theodore Ventrone

    IPC分类号： G06F9/45 ,  G06F12/08 ,  G06F12/00 ,  G06F9/38 ,  G06F13/00

    CPC分类号： G06F8/4442 ,  G06F12/0862 ,  G06F2212/6028

    摘要： An apparatus and method for pre-loading a cache memory based on information contained in a compiler generated program map are disclosed. The program map is generated by the compiler at the time source code is compiled into object code. For each application program, the user would have this program map stored with the object file. At the beginning of the program execution cycle, the operating system will determine whether or not a program map exists for the application. If a program map exists, the operating system will load the program map into an area of RAM designated as the program map random access memory (RAM). The program map will be used to pre-load the cache with the appropriate data and instructions for the central processing unit (CPU) to process. The program mapping would be the address location of each jump/branch target that the CPU might encounter during the execution cycle. Each of these locations represent a starting point for a new code sequence. At the start of the map will be an identifier field to mark the start of the map. The next field in the program map will provide the entry point of the starting address of the application program. If a particular application program does not have a program map, the program and cache operation will remain unchanged. This feature provides backwards compatibility with existing application programs.

    摘要翻译： 公开了一种基于编译器生成的程序映射中包含的信息来预加载高速缓冲存储器的装置和方法。 程序地图由编译器在源代码被编译成目标代码时生成。 对于每个应用程序，用户将该目录文件存储该程序映射。 在程序执行周期开始时，操作系统将确定应用程序是否存在程序映射。 如果存在程序映射，则操作系统将程序映射加载到指定为程序映射随机存取存储器（RAM）的RAM区域中。 程序地图将用于预先加载高速缓存，并具有相应的数据和指令，供中央处理单元（CPU）处理。 程序映射将是执行周期中CPU可能遇到的每个跳转/转移目标的地址位置。 这些位置中的每一个代表新代码序列的起始点。 在地图的开始，将是一个标识符字段来标记地图的开始。 程序地图中的下一个字段将提供应用程序起始地址的入口点。 如果特定的应用程序没有程序映射，程序和缓存操作将保持不变。 此功能提供与现有应用程序的向后兼容性。

    DESIGN STRUCTURE FOR MEASUREMENT OF POWER CONSUMPTION WITHIN AN INTEGRATED CIRCUIT
    9.
    发明申请
    DESIGN STRUCTURE FOR MEASUREMENT OF POWER CONSUMPTION WITHIN AN INTEGRATED CIRCUIT 失效
    在集成电路中测量功耗的设计结构

    公开(公告)号：US20090153324A1

    公开(公告)日：2009-06-18

    申请号：US12046501

    申请日：2008-03-12

    申请人： Kenneth Joseph Goodnow ,  Clarence Rosser Ogilvie ,  Nitin Sharma ,  Sebastian Theodore Ventrone ,  Charles S. Woodruff

    发明人： Kenneth Joseph Goodnow ,  Clarence Rosser Ogilvie ,  Nitin Sharma ,  Sebastian Theodore Ventrone ,  Charles S. Woodruff

    IPC分类号： G08B21/00

    CPC分类号： G01R31/31721

    摘要： An design structure for measuring power consumed during operation of an integrated circuit. The design structure including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal.

    摘要翻译： 一种用于测量集成电路运行期间消耗的功率的设计结构。 该设计结构包括：具有输入和输出的数据处理电路，所述数据处理电路被配置为基于输入数据信号产生输出数据信号; 功率测量电路，被配置为测量由所述输入信号产生所述输出信号时由所述处理电路消耗的电力量;连接在所述处理电路和所述处理电路的电源之间的所述功率测量电路; 以及存储元件，被配置为存储包含表示由处理电路消耗的电力量的值的标签，用于从输入数据信号生成输出数据信号，以及（a）输入数据信号的输入数据或（b ）指向输入数据信号的输入数据的指针。