公开(公告)号：US09159843B2

公开(公告)日：2015-10-13

申请号：US13476356

申请日：2012-05-21

申请人： Kentaro Saito ,  Kazumasa Yanagisawa ,  Yasushi Ishii ,  Koichi Toba

发明人： Kentaro Saito ,  Kazumasa Yanagisawa ,  Yasushi Ishii ,  Koichi Toba

IPC分类号： H01L29/778 ,  H01L21/336 ,  H01L29/792 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  G11C16/04

CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/66833

摘要： To improve the electric performance and reliability of a semiconductor device. A memory gate electrode of a split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 6a and a silicon film 6b over the metal film 6a. In an upper end part of the metal film 6a, a metal oxide portion 17 is formed by oxidation of a part of the metal film 6a. A control gate electrode of the split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 4a and the silicon film 4b over the metal film 4a.

摘要翻译： 提高半导体器件的电气性能和可靠性。 分闸式非易失性存储器的存储栅极是由金属膜6a上的金属膜6a和硅膜6b的叠层膜形成的金属栅电极。 在金属膜6a的上端部分，通过氧化金属膜6a的一部分而形成金属氧化物部分17。 分闸式非易失性存储器的控制栅电极是由金属膜4a的叠层膜和金属膜4a上的硅膜4b形成的金属栅电极。

公开(公告)号：US20100237404A1

公开(公告)日：2010-09-23

申请号：US12718002

申请日：2010-03-05

申请人： KOICHI TOBA ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

发明人： KOICHI TOBA ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7885

摘要： A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.

摘要翻译： 公开了一种具有非易失性存储器的半导体器件，其干扰缺陷可被减弱或防止。 非易失性存储器的存储单元具有通过用于电荷存储的绝缘膜形成在半导体衬底的主表面上的存储栅电极。 第一侧壁形成在存储栅电极的侧面上，在第一侧壁的侧面形成有第二侧壁。 在存储单元中用于源极的n +型半导体区域的上表面上形成硅化物层，其存储栅极电极MG侧的端部由第二侧壁限定。

公开(公告)号：US07863670B2

公开(公告)日：2011-01-04

申请号：US12490147

申请日：2009-06-23

申请人： Yasushi Ishii ,  Takashi Hashimoto ,  Yoshiyuki Kawashima ,  Koichi Toba ,  Satoru Machida ,  Kozo Katayama ,  Kentaro Saito ,  Toshikazu Matsui

发明人： Yasushi Ishii ,  Takashi Hashimoto ,  Yoshiyuki Kawashima ,  Koichi Toba ,  Satoru Machida ,  Kozo Katayama ,  Kentaro Saito ,  Toshikazu Matsui

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/6653

摘要： In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrode 14 of the low withstand voltage MISFET and the ratio of thickness of a memory gate with respect to the gate length of the memory gate is larger than 1. The control gate and a gate electrode 15 are formed in a multilayer structure including an electrode material film 8A and an electrode material layer 8B, and the gate electrode 14 is a single layer structure formed at the same time as the electrode material film 8A of the control gate.

摘要翻译： 在包括具有控制栅极和存储器栅极的分离栅极型存储单元，低耐压MISFET和高耐压MISFET的半导体器件中，抑制了存储单元的阈值电压的变化。 控制栅极的栅极绝缘膜比高耐压MISFET的栅极绝缘膜薄，控制栅极比低耐压MISFET的栅电极14厚，存储栅的厚度比相对于 存储器栅极的栅极长度大于1.控制栅极和栅电极15形成为包括电极材料膜8A和电极材料层8B的多层结构，并且栅电极14是形成的单层结构 同时作为控制栅极的电极材料膜8A。

公开(公告)号：US07745288B2

公开(公告)日：2010-06-29

申请号：US11717053

申请日：2007-03-13

申请人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

发明人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

IPC分类号： H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7885

摘要： A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.

摘要翻译： 公开了一种具有非易失性存储器的半导体器件，其干扰缺陷可被减弱或防止。 非易失性存储器的存储单元具有通过用于电荷存储的绝缘膜形成在半导体衬底的主表面上的存储栅电极。 第一侧壁形成在存储栅电极的侧面上，在第一侧壁的侧面形成有第二侧壁。 在存储单元中用于源极的n +型半导体区域的上表面上形成硅化物层，其存储栅极电极MG侧的端部由第二侧壁限定。

公开(公告)号：US20070262382A1

公开(公告)日：2007-11-15

申请号：US11727591

申请日：2007-03-27

申请人： Yasushi Ishii ,  Takashi Hashimoto ,  Yoshiyuki Kawashima ,  Koichi Toba ,  Satoru Machida ,  Kozo Katayama ,  Kentaro Saito ,  Toshikazu Matsui

发明人： Yasushi Ishii ,  Takashi Hashimoto ,  Yoshiyuki Kawashima ,  Koichi Toba ,  Satoru Machida ,  Kozo Katayama ,  Kentaro Saito ,  Toshikazu Matsui

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392 ,  H01L21/8234 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/6653

摘要： In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrode 14 of the low withstand voltage MISFET and the ratio of thickness of a memory gate with respect to the gate length of the memory gate is larger than 1. The control gate and a gate electrode 15 are formed in a multilayer structure including an electrode material film 8A and an electrode material layer 8B, and the gate electrode 14 is a single layer structure formed at the same time as the electrode material film 8A of the control gate.

摘要翻译： 在包括具有控制栅极和存储器栅极的分离栅极型存储单元，低耐压MISFET和高耐压MISFET的半导体器件中，抑制了存储单元的阈值电压的变化。 控制栅极的栅极绝缘膜比高耐压MISFET的栅极绝缘膜薄，控制栅极比低耐压MISFET的栅电极14厚，存储栅的厚度比相对于 存储器栅极的栅极长度大于1.控制栅极和栅极电极15形成为包括电极材料膜8A和电极材料层8B的多层结构，并且栅电极14是单层 结构与控制门的电极材料膜8A同时形成。

公开(公告)号：US07557005B2

公开(公告)日：2009-07-07

申请号：US11727591

申请日：2007-03-27

申请人： Yasushi Ishii ,  Takashi Hashimoto ,  Yoshiyuki Kawashima ,  Koichi Toba ,  Satoru Machida ,  Kozo Katayama ,  Kentaro Saito ,  Toshikazu Matsui

发明人： Yasushi Ishii ,  Takashi Hashimoto ,  Yoshiyuki Kawashima ,  Koichi Toba ,  Satoru Machida ,  Kozo Katayama ,  Kentaro Saito ,  Toshikazu Matsui

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/6653

摘要： In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrode 14 of the low withstand voltage MISFET and the ratio of thickness of a memory gate with respect to the gate length of the memory gate is larger than 1. The control gate and a gate electrode 15 are formed in a multilayer structure including an electrode material film 8A and an electrode material layer 8B, and the gate electrode 14 is a single layer structure formed at the same time as the electrode material film 8A of the control gate.

摘要翻译： 在包括具有控制栅极和存储器栅极的分离栅极型存储单元，低耐压MISFET和高耐压MISFET的半导体器件中，抑制了存储单元的阈值电压的变化。 控制栅极的栅极绝缘膜比高耐压MISFET的栅极绝缘膜薄，控制栅极比低耐压MISFET的栅电极14厚，存储栅的厚度比相对于 存储器栅极的栅极长度大于1.控制栅极和栅电极15形成为包括电极材料膜8A和电极材料层8B的多层结构，并且栅电极14是形成的单层结构 同时作为控制栅极的电极材料膜8A。

公开(公告)号：US08530958B2

公开(公告)日：2013-09-10

申请号：US12718002

申请日：2010-03-05

申请人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

发明人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

IPC分类号： H01L29/792

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7885

摘要： A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.

摘要翻译： 公开了一种具有非易失性存储器的半导体器件，其干扰缺陷可被减弱或防止。 非易失性存储器的存储单元具有通过用于电荷存储的绝缘膜形成在半导体衬底的主表面上的存储栅电极。 第一侧壁形成在存储栅电极的侧面上，在第一侧壁的侧面形成有第二侧壁。 在存储单元中用于源极的n +型半导体区域的上表面上形成硅化物层，其存储栅极电极MG侧的端部由第二侧壁限定。

公开(公告)号：US20070228446A1

公开(公告)日：2007-10-04

申请号：US11717053

申请日：2007-03-13

申请人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

发明人： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Kentaro Saito ,  Toshikazu Matsui ,  Takashi Hashimoto ,  Kosuke Okuyama

IPC分类号： H01L29/76

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7885

摘要： A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.

摘要翻译： 公开了一种具有非易失性存储器的半导体器件，其干扰缺陷可被减弱或防止。 非易失性存储器的存储单元具有通过用于电荷存储的绝缘膜形成在半导体衬底的主表面上的存储栅电极。 第一侧壁形成在存储栅电极的侧面上，在第一侧壁的侧面形成有第二侧壁。 在存储单元中用于源极的n + + / - 型半导体区域的上表面上形成硅化物层，其存储栅电极MG侧的端部由第二侧壁限定。

公开(公告)号：US20110008943A1

公开(公告)日：2011-01-13

申请号：US12885086

申请日：2010-09-17

申请人： Koichi TOBA ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Takashi Hashimoto ,  Kosuke Okuyama

发明人： Koichi TOBA ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Takashi Hashimoto ,  Kosuke Okuyama

IPC分类号： H01L21/8239

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

摘要： The present invention provides a technology capable of reducing an area occupied by a nonvolatile memory while improving the reliability of the nonvolatile memory. In a semiconductor device, the structure of a code flash memory cell is differentiated from that of a data flash memory cell. More specifically, in the code flash memory cell, a memory gate electrode is formed only over the side surface on one side of a control gate electrode to improve a reading speed. In the data flash memory cell, on the other hand, a memory gate electrode is formed over the side surfaces on both sides of a control gate electrode. By using a multivalued memory cell instead of a binary memory cell, the resulting data flash memory cell can have improved reliability while preventing deterioration of retention properties and reduce its area.

摘要翻译： 本发明提供一种能够在提高非易失性存储器的可靠性的同时减少由非易失性存储器占据的面积的技术。 在半导体器件中，代码闪存单元的结构与数据闪存单元的结构不同。 更具体地，在代码闪速存储单元中，仅在控制栅电极的一侧的侧面上形成存储栅电极，以提高读取速度。 另一方面，在数据闪存单元中，在控制栅电极的两侧的侧面上形成存储栅电极。 通过使用多值存储单元而不是二进制存储单元，所得到的数据闪存单元可以提高可靠性，同时防止保留性能的劣化并减小其面积。

公开(公告)号：US08969943B2

公开(公告)日：2015-03-03

申请号：US13302184

申请日：2011-11-22

申请人： Koichi Toba ,  Yasushi Ishii ,  Hiraku Chakihara ,  Kota Funayama ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

发明人： Koichi Toba ,  Yasushi Ishii ,  Hiraku Chakihara ,  Kota Funayama ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L27/115

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/792

摘要： A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

摘要翻译： 提供了具有非易失性存储器的半导体器件，其具有改进的特性。 半导体器件包括控制栅极电极，与控制栅电极相邻设置的存储栅电极，第一绝缘膜和包括电荷存储部分的第二绝缘膜。 在这些部件中，存储栅电极由包括位于第二绝缘膜上的第一硅区的硅膜和位于第一硅区之上的第二硅区构成。 第二硅区域含有p型杂质，第一硅区域的p型杂质浓度低于第二硅区域的p型杂质浓度。