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    Determining relative amount of usage of data retaining device based on potential of charge storing device
    2.
    发明授权
    Determining relative amount of usage of data retaining device based on potential of charge storing device 有权
    基于电荷存储装置的潜力确定数据保存装置的相对使用量

    公开(公告)号：US07869298B2

    公开(公告)日：2011-01-11

    申请号：US12045744

    申请日：2008-03-11

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

    IPC分类号： G11C7/00

    CPC分类号： G06F12/121 ,  G06F12/122

    摘要： A system for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.

    摘要翻译： 公开了一种用于确定数据保持装置的相对使用量的系统。 电荷存储装置以数据保持装置的使用触发电荷存储装置的充电的方式耦合到数据保持装置。 在数据保持装置闲置的期间，由于自然的手段，电荷存储装置中的电荷衰减。 因此，可以使用电荷存储装置的电位来指示数据保持装置的使用量。 可以使用将一对一耦合到两个数据保持装置的两个电荷存储装置的电位的比较作为确定两个数据保持装置中的每一个相对于另一个的相对使用量的基础。

    Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator
    3.
    发明授权
    Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator 失效
    基于部分耗尽的绝缘体上硅的状态确定数据保存装置中数据的历史状态

    公开(公告)号：US07633819B2

    公开(公告)日：2009-12-15

    申请号：US12180776

    申请日：2008-07-28

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

    IPC分类号： G11C29/00

    CPC分类号： G11C11/417

    摘要： A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device.

    摘要翻译： 公开了一种用于确定数据保持装置中的数据的历史状态的系统，方法和程序产品。 耦合到数据保持装置的部分耗尽的绝缘体上硅（PD SOI）器件的状态被测量以指示PD SOI器件的体电压。 PD SOI器件的体电压可以指示PD SOI器件已经空转多长时间，这间接地指示数据保持器件中的数据未被访问多长时间。 因此，本发明可以在数据保留装置的管理中与例如高速缓存替换算法有效地使用。

    Inactivity triggered self clocking logic family
    6.
    发明授权
    Inactivity triggered self clocking logic family 有权
    不活动触发自我计时逻辑家族

    公开(公告)号：US08575964B2

    公开(公告)日：2013-11-05

    申请号：US13426776

    申请日：2012-03-22

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, Jr. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, Jr. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

    IPC分类号： H03K19/00

    CPC分类号： H03K19/0966 ,  H03K19/0013

    摘要： Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.

    摘要翻译： 电路的局部逻辑区域包括电连接到局部电阻电压电路的本地比较器，局部电阻接地电路和局部寄存器结构。 当本地参考电压低于本地电压阈值时，本地比较器会向本地寄存器结构提供时钟脉冲。 本地组合逻辑结构中的活动导致本地参考电压低于局部参考电压，而与全局参考电压的变化无关，导致比较器输出时钟脉冲（具有足够的延迟以允许逻辑结果存储在寄存器中 只有在本地逻辑设备中已经满足设置时间之后）。 这消除了对时钟分配树的需要，从而在局部组合逻辑结构中没有活动时节省功率。

    Processor pipeline architecture logic state retention systems and methods
    7.
    发明授权
    Processor pipeline architecture logic state retention systems and methods 有权
    处理器管道架构逻辑状态保留系统和方法

    公开(公告)号：US07882334B2

    公开(公告)日：2011-02-01

    申请号：US11276236

    申请日：2006-02-20

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

    IPC分类号： G06F15/76 ,  G06F1/00

    CPC分类号： G06F9/3869 ,  G11C27/026

    摘要： A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

    摘要翻译： 公开了一种用于保持处理器流水线架构的逻辑状态的系统，方法和程序产品。 比较器位于处理器流水线架构的两个阶段之间。 存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。 提供了与早期输出值相同的参考逻辑。 逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点处产生逻辑，该逻辑是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态 电容器。 提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

    DETERMINING HISTORY STATE OF DATA IN DATA RETAINING DEVICE BASED ON STATE OF PARTIALLY DEPLETED SILICON-ON-INSULATOR
    8.
    发明申请
    DETERMINING HISTORY STATE OF DATA IN DATA RETAINING DEVICE BASED ON STATE OF PARTIALLY DEPLETED SILICON-ON-INSULATOR 失效
    根据部分绝缘硅绝缘体的状态确定数据保留装置中数据的历史状态

    公开(公告)号：US20080285338A1

    公开(公告)日：2008-11-20

    申请号：US12180776

    申请日：2008-07-28

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

    IPC分类号： G11C11/34

    CPC分类号： G11C11/417

    摘要： A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device.

    摘要翻译： 公开了一种用于确定数据保持装置中的数据的历史状态的系统，方法和程序产品。 耦合到数据保持装置的部分耗尽的绝缘体上硅（PD SOI）器件的状态被测量以指示PD SOI器件的体电压。 PD SOI器件的体电压可以指示PD SOI器件已经空转多长时间，这间接地指示数据保持器件中的数据未被访问多长时间。 因此，本发明可以在数据保留装置的管理中与例如高速缓存替换算法有效地使用。

    DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE
    9.
    发明申请
    DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE 有权
    基于充电储存装置的可能性确定使用数据保留装置的相对数量

    公开(公告)号：US20080151672A1

    公开(公告)日：2008-06-26

    申请号：US12045744

    申请日：2008-03-11

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

    IPC分类号： G11C7/00

    CPC分类号： G06F12/121 ,  G06F12/122

    摘要： A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.

    摘要翻译： 公开了一种用于确定数据保留装置的相对使用量的系统，方法和程序产品。 电荷存储装置以数据保持装置的使用触发电荷存储装置的充电的方式耦合到数据保持装置。 在数据保持装置闲置的期间，由于自然的手段，电荷存储装置中的电荷衰减。 因此，可以使用电荷存储装置的电位来指示数据保持装置的使用量。 可以使用将一对一耦合到两个数据保持装置的两个电荷存储装置的电位的比较作为确定两个数据保持装置中的每一个相对于另一个的相对使用量的基础。

    Processor pipeline architecture logic state retention systems and methods
    10.
    发明授权
    Processor pipeline architecture logic state retention systems and methods 有权
    处理器管道架构逻辑状态保留系统和方法

    公开(公告)号：US07937560B2

    公开(公告)日：2011-05-03

    申请号：US12121292

    申请日：2008-05-15

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

    IPC分类号： G06F15/76 ,  G06F1/00

    CPC分类号： G06F9/3867 ,  G06F1/32 ,  G06F1/3287 ,  G06F11/1407 ,  G06F11/1441 ,  Y02D10/171

    摘要： A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

    摘要翻译： 公开了一种用于保留处理器流水线架构的逻辑状态的解决方案。 比较器位于处理器流水线架构的两个阶段之间。 存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。 提供了与早期输出值相同的参考逻辑。 逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点产生逻辑，该参考节点是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态 电容器。 提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。