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公开(公告)号：US06989229B2
公开(公告)日：2006-01-24
申请号：US10400347
申请日：2003-03-27
IPC分类号： G03F7/20
CPC分类号： G03F7/70941 , G03F1/36 , G03F1/70 , G03F7/70433 , H01L21/0274
摘要： Photoresist on a wafer is exposed using tiles on a mask that improve flare performance. Features that are not to be exposed on the photoresist correspond to features on the mask. The various features are surrounded by other features that vary and thus affect flare differently. Selected features have tiles added nearby but also far enough away to improve uniformity in the effects of flare on the various features that are intended to be present in the photoresist. The tiles are made either very small in width or partially absorbing so that the tiles are not resolved in the photoresist. Thus the tiles reduce flare but do not alter the desired pattern in the photoresist.
摘要翻译： 晶片上的光致抗蚀剂使用掩模上的瓷砖进行曝光，从而改善光斑性能。 在光刻胶上不暴露的特征对应于掩模上的特征。 各种特征被不同的其他特征所包围，从而不同地影响耀斑。 选定的特征具有附近附近的瓷砖，但也足够远，以改善光斑对预期存在于光致抗蚀剂中的各种特征的影响的均匀性。 瓷砖制成的宽度非常小或部分吸收，使得瓷砖未在光致抗蚀剂中分辨。 因此，瓷砖减少了光斑，但不改变光刻胶中所需的图案。
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2.发明授权Method for manufacturing a lithographic reticle for transferring an integrated circuit design to a semiconductor wafer 有权用于制造用于将集成电路设计转移到半导体晶片的光刻掩模版的方法公开(公告)号：US06649452B2
公开(公告)日：2003-11-18
申请号：US10085960
申请日：2002-02-28
IPC分类号： H01L2182
摘要： A lithographic reticle with subresolution features in the design-pattern is used to control critical dimensions in a semiconductor manufacturing process. After the location of design and processing features is determined, subresolution features are formed in areas devoid of design and processing features. The subresolution features can substantially fill all of the area devoid of design processing features or, instead, selectively fill portions of the area. In one embodiment, the width of the area devoid of design and processing features is less than two times the width of a feature. The presence of the subresolution features results in improved control of small dimensions of features in semiconductor processing, thereby increasing yield and device performance.
摘要翻译： 在设计图案中具有亚分辨特征的光刻掩模版用于控制半导体制造工艺中的关键尺寸。 在确定设计和处理特征的位置之后，在不具有设计和处理特征的区域中形成分解特征。 分解特征可以基本上填满没有设计处理特征的所有区域，或者相反地，选择性地填充该区域的部分。 在一个实施例中，没有设计和处理特征的区域的宽度小于特征宽度的两倍。 分解特征的存在导致对半导体处理中的特征的小尺寸的改进的控制，从而增加产量和装置性能。
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公开(公告)号：US06287951B1
公开(公告)日：2001-09-11
申请号：US09206715
申请日：1998-12-07
申请人： Kevin D. Lucas , Christopher D. Pettinato , Wayne D. Clark , Stanley M. Filipiak , Yeong Jyh Lii
发明人： Kevin D. Lucas , Christopher D. Pettinato , Wayne D. Clark , Stanley M. Filipiak , Yeong Jyh Lii
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/76801 , H01L21/76802 , H01L21/76834 , H01L21/76895
摘要： A hardmask layer (34) is formed over insulating layers (26, 24, 22 and 20), and an antireflective layer (36) is formed overlying the hardmask layer (34). A resist layer (38) is formed overlying the antireflective layer (36), and an opening is formed in the resist layer to expose a surface portion of the antireflective layer (36). The exposed surface portion of the antireflective layer (36) and portions of the hardmask layer (34) are etched to expose a surface portion of the insulating layers (26, 24, 22 and 20), and a feature opening (61) is formed in the insulating layers (26, 24, 22 and 20). A conductive material (74) is deposited to fill the feature opening (61), and portions of the conductive material (74) lying outside the opening are removed.
摘要翻译： 在绝缘层（26,24,22和20）上形成硬掩模层（34），并且形成覆盖在硬掩模层（34）上的抗反射层（36）。 在抗反射层（36）上形成抗蚀剂层（38），在抗蚀剂层上形成开口以露出抗反射层（36）的表面部分。 对抗反射层（36）的暴露表面部分和硬掩模层（34）的部分进行蚀刻以暴露绝缘层（26,24,22和20）的表面部分，形成特征开口（61） 在绝缘层（26,24,22和20）中。 沉积导电材料（74）以填充特征开口（61），并且去除位于开口外侧的导电材料（74）的部分。
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4.发明授权Process for producing and inspecting a lithographic reticle and fabricating semiconductor devices using same 失效用于制造和检查光刻掩模版并使用其制造半导体器件的方法
公开(公告)号：US5849440A
公开(公告)日：1998-12-15
申请号：US792670
申请日：1997-01-29
IPC分类号： G03F1/00 , G03F1/84 , G03F7/20 , H01L21/027 , G03F9/00
CPC分类号： G03F7/705 , G03F1/84 , G03F7/70433 , G03F7/70633
摘要： A process for fabricating a semiconductor device includes the formation of a lithographic reticle (20) having a lithographic pattern (18) overlying a reticle substrate (10). In one embodiment, a reticle inspection database incorporates altered resolution assisting features (30,32) to inspect the lithographic pattern (18). The dimensional difference between the reticle inspection database and the lithographic reticle is substantially equal to the process bias realized during reticle fabrication. Inspection of the lithographic reticle (20) using a reticle inspection database containing altered resolution assisting features reduces the false detection of defects and provides increased sensitivity in the reticle inspection process.
摘要翻译： 一种用于制造半导体器件的工艺包括形成具有覆盖在掩模版衬底（10）上的平版印刷图案（18）的光刻掩模版（20）。 在一个实施例中，掩模版检查数据库包含改变的分辨率辅助特征（30,32）以检查光刻图案（18）。 标线检查数据库和光刻掩模版之间的尺寸差异基本上等于在掩模版制造期间实现的工艺偏差。 使用包含改变的分辨率辅助特征的掩模版检查数据库对光刻掩模版（20）的检查减少了缺陷的错误检测并且在掩模版检查过程中提供了增加的灵敏度。
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5.发明申请METHOD AND APPARATUS FOR DETERMINING MASK LAYOUTS FOR A SPACER-IS-DIELECTRIC SELF-ALIGNED DOUBLE-PATTERNING PROCESS 有权用于确定间隔电介质自对准双向图案的掩模层的方法和装置公开(公告)号：US20120137261A1
公开(公告)日：2012-05-31
申请号：US12955670
申请日：2010-11-29
申请人： Yonchan Ban , Kevin D. Lucas
发明人： Yonchan Ban , Kevin D. Lucas
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Methods and apparatuses are described for determining mask layouts for printing a design intent on a wafer using a spacer-is-dielectric self-aligned double-patterning process. A system can determine whether a graph corresponding to a design intent is two-colorable. If the graph is not two-colorable, the system can merge one or more pairs of shapes in the design intent to obtain a modified design intent, so that a modified graph corresponding to the modified design intent is two-colorable. The system can then determine a two-coloring for the modified graph. Next, the system can place one or more core shapes in a mandrel mask layout which correspond to vertices in the modified graph that are associated with a selected color in the two-coloring. The system can then place one or more shapes in a trim mask layout for separating the shapes in the design intent that were merged.
摘要翻译： 描述了用于确定用于使用间隔物 - 电介质自对准双图案化工艺在晶片上印刷设计意图的掩模布局的方法和装置。 系统可以确定对应于设计意图的图形是否是可双色的。 如果图形不是双色的，则系统可以在设计意图中合并一对或多对形状以获得修改的设计意图，使得对应于修改后的设计意图的修改后的图形是双色的。 然后，系统可以确定修改图的双色。 接下来，系统可以将一个或多个核心形状放置在心轴掩模布局中，心轴掩模布局对应于在双色中与选定颜色相关联的修改图中的顶点。 然后，系统可以将一个或多个形状放在修剪蒙版布局中，以分离合并的设计意图中的形状。
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公开(公告)号：US06818362B1
公开(公告)日：2004-11-16
申请号：US10782566
申请日：2004-02-19
申请人： Kevin D. Lucas , Robert E. Boone , Lloyd C. Litt , Wei E. Wu
发明人： Kevin D. Lucas , Robert E. Boone , Lloyd C. Litt , Wei E. Wu
IPC分类号： G03F900
摘要： A method of generating a design of a reticle for a photolithography process. The reticle may include phase shift features, binary features, and mixed features. The method includes generating a reticle design from a pattern layout and then optimizing the reticle design. In some examples, generating the reticle design includes binning the features of the layout based on feature width. Examples of optimization operations include an over/under operation, an under/over operation, a feature segment expansion operation, a feature edge portion conversation from a binary portion to a phase shift portion, a corner binary segment expansion, a discontinuity removal operation, and a feature dimension change operation that includes a determination of a Mask Error Factor (MEF).
摘要翻译： 一种产生光刻工艺的掩模版设计的方法。 标线片可以包括相移特征，二进制特征和混合特征。 该方法包括从图案布局生成掩模版设计，然后优化掩模版设计。 在一些示例中，生成掩模版设计包括基于特征宽度来组合布局的特征。 优化操作的示例包括过/下操作，下/过操作，特征段扩展操作，从二进制部分到相移部分的特征边缘部分对话，角二进制段扩展，不连续删除操作和 特征尺寸变化操作，其包括掩模误差因子（MEF）的确定。
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7.发明授权Method and apparatus for determining mask layouts for a spacer-is-dielectric self-aligned double-patterning process 有权用于确定间隔物电介质自对准双图案化工艺的掩模布局的方法和装置公开(公告)号：US08312394B2
公开(公告)日：2012-11-13
申请号：US12955670
申请日：2010-11-29
申请人： Yonchan Ban , Kevin D. Lucas
发明人： Yonchan Ban , Kevin D. Lucas
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Methods and apparatuses are described for determining mask layouts for printing a design intent on a wafer using a spacer-is-dielectric self-aligned double-patterning process. A system can determine whether a graph corresponding to a design intent is two-colorable. If the graph is not two-colorable, the system can merge one or more pairs of shapes in the design intent to obtain a modified design intent, so that a modified graph corresponding to the modified design intent is two-colorable. The system can then determine a two-coloring for the modified graph. Next, the system can place one or more core shapes in a mandrel mask layout which correspond to vertices in the modified graph that are associated with a selected color in the two-coloring. The system can then place one or more shapes in a trim mask layout for separating the shapes in the design intent that were merged.
摘要翻译： 描述了用于确定用于使用间隔物 - 电介质自对准双图案化工艺在晶片上印刷设计意图的掩模布局的方法和装置。 系统可以确定对应于设计意图的图形是否是可双色的。 如果图形不是双色的，则系统可以在设计意图中合并一对或多对形状以获得修改的设计意图，使得对应于修改后的设计意图的修改后的图形是双色的。 然后，系统可以确定修改图的双色。 接下来，系统可以将一个或多个核心形状放置在心轴掩模布局中，心轴掩模布局对应于在双色中与选定颜色相关联的修改图中的顶点。 然后，系统可以将一个或多个形状放在修剪蒙版布局中，以分离合并的设计意图中的形状。
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公开(公告)号：US20080250374A1
公开(公告)日：2008-10-09
申请号：US12067583
申请日：2005-09-20
申请人： Kevin D. Lucas , Robert E. Boone , Karl Wimmer , Kyle Patterson
发明人： Kevin D. Lucas , Robert E. Boone , Karl Wimmer , Kyle Patterson
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method is provided for making an integrated circuit. Cell representing a layout of a set of features, is divided into at least a first region and a second region. Optical Proximity Correction is carried out on at least the first region of cell. One or more instances of cell are located to define IC prior to carrying out final OPC optimisation on the second regions of each cell in the defined IC.
摘要翻译： 提供了一种制造集成电路的方法。 表示一组特征的布局的单元被划分为至少第一区域和第二区域。 至少在细胞的第一区域进行光学邻近校正。 定位单元的一个或多个实例以在对所定义的IC中的每个单元的第二区域进行最终OPC优化之前定义IC。
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公开(公告)号：US07284231B2
公开(公告)日：2007-10-16
申请号：US11018637
申请日：2004-12-21
申请人： Kevin D. Lucas , Robert E. Boone , Mehul D. Shroff , Kirk J. Strozewski , Chi-Min Yuan , Jason T. Porter
发明人： Kevin D. Lucas , Robert E. Boone , Mehul D. Shroff , Kirk J. Strozewski , Chi-Min Yuan , Jason T. Porter
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features widths, feature spaces or feature enclosures being patterned smaller than designed. In some embodiments, the upsized features are larger in the wafer circuit pattern than are drawn in a designed database. The method for improving manufacturability of a design, in some embodiments, is stored on a computer readable storage medium.
摘要翻译： 一种用于改进设计的可制造性的方法包括在布局设计的多个交互层上执行空间或外壳检查，然后使用所得到的空间或外壳数据来移动改变的设计数据库中的预定特征边缘以降低特征宽度，特征 图案的空间或特征外壳图案比设计的小。 在一些实施例中，晶片电路图案中的大尺寸特征比在设计的数据库中绘制的特征更大。 在一些实施例中，用于提高设计的可制造性的方法被存储在计算机可读存储介质上。
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公开(公告)号：US06783904B2
公开(公告)日：2004-08-31
申请号：US10150564
申请日：2002-05-17
IPC分类号： G03F900
CPC分类号： G03F1/36 , G03F7/70433 , G03F7/705
摘要： A method (10) for correcting lithography error includes generating (18) data that defines relationships between at least one predetermined design layout parameter and a known minimum required lithographic process capability (e.g. minimum feature spacing), and then using the data to upsize (30) predetermined isolated features or portions of predetermined isolated or semi-isolated features. In some embodiments, the resulting wafer circuit pattern (70) has isolated features (71, 72, 74) that are all larger than a predetermined minimum width. The upsized features are larger in the wafer circuit pattern (70) than they are drawn in a designed database. The method for correcting the lithography error, in some embodiments, is stored on a computer readable storage medium.
摘要翻译： 用于校正光刻误差的方法（10）包括生成（18）定义至少一个预定设计布局参数和已知最小要求光刻处理能力（例如最小特征间距）之间的关系的数据，然后使用该数据来增大（30 ）预定隔离特征或预定隔离或半隔离特征的部分。 在一些实施例中，所得到的晶片电路图案（70）具有均大于预定最小宽度的隔离特征（71,72,74）。 晶片电路图案（70）中的大尺寸特征比在设计的数据库中绘制的特征更大。 在一些实施例中，用于校正光刻误差的方法被存储在计算机可读存储介质上。
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