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    Magnetoresistive Random Access Memory Device and Method of Manufacturing the Same
    4.
    发明申请
    Magnetoresistive Random Access Memory Device and Method of Manufacturing the Same 审中-公开
    磁阻随机存取存储器件及其制造方法

    公开(公告)号：US20170054070A1

    公开(公告)日：2017-02-23

    申请号：US15146355

    申请日：2016-05-04

    申请人： Jung-Hoon Bak ,  Myoung-Su Son ,  Jae-Chul Shim ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

    发明人： Jung-Hoon Bak ,  Myoung-Su Son ,  Jae-Chul Shim ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

    IPC分类号： H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L43/08

    CPC分类号： H01L43/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

    摘要： In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.

    摘要翻译： 在制造MRAM器件的方法中，在衬底上形成包括下电极，MTJ结构和顺序层叠的上电极的存储单元。 在衬底上形成包括依次堆叠的覆盖层，牺牲层和蚀刻停止层的保护层结构以覆盖存储单元。 在保护层结构上形成绝缘中间层。 形成绝缘中间层以形成露出保护层结构的开口。 暴露的保护层结构被部分去除以暴露上电极。 在暴露的上电极上形成布线以填充开口。

    Semiconductor device having ferroelectric material capacitor and method of making the same
    9.
    发明授权
    Semiconductor device having ferroelectric material capacitor and method of making the same 失效

    公开(公告)号：US07498179B2

    公开(公告)日：2009-03-03

    申请号：US11218972

    申请日：2005-09-02

    申请人： Yoon-Jong Song

    发明人： Yoon-Jong Song

    IPC分类号： H01L21/00

    CPC分类号： H01L27/11502 ,  H01L21/28568 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

    摘要： The present invention relates to the field of a semiconductor device having a ferroelectric material capacitor and method of making the same. The semiconductor device includes a capacitor having a triple-level oxygen barrier layer pattern formed by an oxygen barrier metal layer, a material layer formed of a conductive solid solution by compounding the oxygen barrier metal layer and oxygen, and an oxygen barrier metal on an interlayer dielectric with a contact plug. The capacitor also has an electrode and a ferroelectric film electrically contacting to the oxygen barrier layer.Further, a wetting layer is formed between the oxygen barrier layer and the contact plug, and an iridium oxygen layer is formed between the oxygen barrier layer and a capacitor electrode.

    PRAMs having a plurality of active regions located vertically in sequence and methods of forming the same
    10.
    发明申请
    PRAMs having a plurality of active regions located vertically in sequence and methods of forming the same 有权
    具有多个有序区域的垂直位置的PRAM及其形成方法

    公开(公告)号：US20060076548A1

    公开(公告)日：2006-04-13

    申请号：US11246863

    申请日：2005-10-07

    申请人： Jae-Hyun Park ,  Hyeong-Geun An ,  Su-Jin Ahn ,  Yoon-Jong Song ,  Hyung-Joo Youn ,  Kyu-Chul Kim

    发明人： Jae-Hyun Park ,  Hyeong-Geun An ,  Su-Jin Ahn ,  Yoon-Jong Song ,  Hyung-Joo Youn ,  Kyu-Chul Kim

    IPC分类号： H01L29/02

    CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/144

    摘要： There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.

    摘要翻译： 提供了具有顺序定位的多个活性区域和其形成方法的PRAMS。 PRAM和该方法提供了用给定设计规则快速改变相变层图案中的相位的方法。 在单元阵列区域和外围电路区域中制备限定至少一个参考有源区的半导体衬底。 在通过参考有源区域的主表面的垂直线上的其它半导体衬底依次定位。 其他半导体衬底分别限定其它有源区。 在参考有源区的半导体衬底上形成下电池栅极图案，并且上电池栅极图案分别设置在其它有源区的其它半导体衬底上。