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44 条记录 (耗时 0.016 秒)

    Method for fabricating an integrated circuit capacitor
    6.
    发明授权
    Method for fabricating an integrated circuit capacitor 有权
    集成电路电容器的制造方法

    公开(公告)号：US06479850B2

    公开(公告)日：2002-11-12

    申请号：US09968884

    申请日：2001-10-03

    申请人： Ki-Young Lee

    发明人： Ki-Young Lee

    IPC分类号： H01L27108

    CPC分类号： H01L28/40 ,  H01L28/60 ,  H01L28/75 ,  Y10S438/978

    摘要： A method for fabricating a MIM capacitor of a MDL logic or analog circuit of a semiconductor device. A conductivity layer is formed on a semiconductor substrate having a first inter-level insulating layer. A capping metal layer having an etching rate higher than an oxide layer is formed on the conductivity layer. A lower electrode comprising a “conductivity layer/capping metal layer” deposition is formed by selectively etching the capping metal layer and the conductivity layer in order to expose a predetermined part of the surface of the first inter-level insulating layer. A second inter-level insulating layer is formed on the first inter-level insulating layer covering the lower electrode. A via hole is formed by selectively etching both the second inter-level insulating layer and the lower electrode thereby to expose a portion of the lower electrode so that a tapered capping metal layer remains along the lower edges of the via hole. A dielectric layer, devoid of step coverage defects and concentrated electric fields, is inserted in the via hole between the lower and upper electrodes thereby preventing current leakage and short circuits at portions of the dielectric layer. This has the beneficial effect of substantially improving product yield and reliability.

    摘要翻译： 一种用于制造半导体器件的MDL逻辑或模拟电路的MIM电容器的方法。 在具有第一层间绝缘层的半导体衬底上形成导电层。 在导电层上形成具有高于氧化物层的蚀刻速率的覆盖金属层。 通过选择性地蚀刻封盖金属层和导电层来形成包括“导电层/覆盖金属层”沉积的下电极，以暴露第一层间绝缘层的表面的预定部分。 在覆盖下电极的第一层间绝缘层上形成第二层间绝缘层。 通过选择性地蚀刻第二层间绝缘层和下电极来形成通孔，从而露出下电极的一部分，使得锥形封盖金属层沿着通孔的下边缘保留。 在上下电极之间的通孔中插入没有台阶覆盖缺陷和集中电场的电介质层，从而防止电介质层部分的电流泄漏和短路。 这具有显着提高产品产量和可靠性的有益效果。

    Methods for forming integrated circuit capacitors including dual electrode depositions
    7.
    发明授权
    Methods for forming integrated circuit capacitors including dual electrode depositions 失效
    用于形成集成电路电容器的方法包括双电极沉积

    公开(公告)号：US5918135A

    公开(公告)日：1999-06-29

    申请号：US867070

    申请日：1997-06-02

    申请人： Ki-Young Lee ,  Kwang-Dong Yoo

    发明人： Ki-Young Lee ,  Kwang-Dong Yoo

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L29/00 ,  H01L21/20

    CPC分类号： H01L28/60

    摘要： A method for forming an integrated circuit device includes the steps of forming a first capacitor electrode on a substrate and forming a first wiring electrode on the substrate. An insulating layer is formed on the first capacitor electrode and on the first wiring electrode opposite the substrate. A second capacitor electrode is formed on a portion of the insulating layer opposite the first capacitor electrode. A contact hole is formed in the insulating layer exposing a portion of the first wiring electrode. A second wiring electrode is then formed on the exposed portion of the wiring electrode, after forming the second capacitor electrode. Related structures are also discussed.

    摘要翻译： 一种形成集成电路器件的方法包括以下步骤：在衬底上形成第一电容器电极，并在衬底上形成第一布线电极。 绝缘层形成在第一电容器电极上和与基板相对的第一布线电极上。 第二电容器电极形成在与第一电容器电极相对的绝缘层的一部分上。 在绝缘层中形成暴露第一布线电极的一部分的接触孔。 在形成第二电容器电极之后，在布线电极的露出部分上形成第二布线电极。 还讨论了相关结构。

    SEMICONDUCTOR DEVICE HAVING FUSE AND CAPACITOR AT THE SAME LEVEL AND METHOD OF FABRICATING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE HAVING FUSE AND CAPACITOR AT THE SAME LEVEL AND METHOD OF FABRICATING THE SAME 失效
    具有同一水平的保险丝和电容器的半导体器件及其制造方法

    公开(公告)号：US20070224771A1

    公开(公告)日：2007-09-27

    申请号：US11755193

    申请日：2007-05-30

    申请人： Seung-Han Park ,  Ki-Young Lee

    发明人： Seung-Han Park ,  Ki-Young Lee

    IPC分类号： H01L29/00

    CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L23/5256 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a semiconductor device and a method of fabricating the same, a fuse and a capacitor are formed at a same level on a semiconductor substrate having a fuse area and a capacitor area. The fuse is placed on the fuse area, and a lower plate is placed on the capacitor area. The lower plate is located on a same plane as the fuse. Further, an upper plate is located above the lower plate, and a capping layer is interposed between the lower plate and the upper plate. Therefore, the fuse and the capacitor can be formed at the same time, thereby minimizing photolithography and etch process steps.

    摘要翻译： 在半导体器件及其制造方法中，在具有熔丝区域和电容器面积的半导体衬底上，在同一电平上形成熔丝和电容器。 保险丝放置在保险丝区域上，下电极放置在电容器区域上。 下板位于与保险丝相同的平面上。 此外，上板位于下板的上方，并且在下板和上板之间插入有盖层。 因此，可以同时形成熔丝和电容器，从而使光刻和蚀刻工艺步骤最小化。

    Method for preparing lithium manganese spinel oxide having improved electrochemical performance
    9.
    发明授权
    Method for preparing lithium manganese spinel oxide having improved electrochemical performance 有权
    制备具有改善的电化学性能的锂锰尖晶石氧化物的方法

    公开(公告)号：US06929788B2

    公开(公告)日：2005-08-16

    申请号：US09913428

    申请日：2000-12-15

    申请人： Hong-Kyu Park ,  Seong-Yong Park ,  Ki-Young Lee ,  Joon-Sung Bae

    发明人： Hong-Kyu Park ,  Seong-Yong Park ,  Ki-Young Lee ,  Joon-Sung Bae

    IPC分类号： C01G45/12 ,  C01G45/00 ,  H01M4/505 ,  H01M10/05 ,  C01G45/02

    CPC分类号： H01M4/505 ,  C01G45/1242 ,  C01P2002/32 ,  C01P2004/03 ,  C01P2004/51 ,  C01P2004/53 ,  C01P2006/40

    摘要： The present invention relates to a method for preparing a lithium manganese complex oxide Li1+xMn2−xO4 (0≦x≦0.12) used as a cathode active material of a lithium or lithium ion secondary battery.The present invention provides a method for preparing a manganese compound comprising the step of simultaneously applying a mechanical force and heat energy to a manganese compound to remove defects present in particles of the manganese compound and to control the aggregation of particles and the shape of the aggregated particles, a method for preparing a lithium manganese complex oxide with a spinel structure using the manganese compound prepared by the above method as a raw material, and a lithium or lithium ion secondary battery using the lithium manganese complex oxide with a spinel structure prepared by the above method as a cathode active material.A lithium or lithium ion secondary battery using the lithium manganese complex oxide with a spinel structure prepared from the manganese compound without defects inside particles as a cathode active material has excellent charge/discharge characteristics and cyclic performance.

    摘要翻译： 本发明涉及一种锂锰复合氧化物Li 1 + x 2 O 2-x O 4（0≤x≤0.4）的制备方法， <= 0.12）用作锂或锂离子二次电池的正极活性物质。 本发明提供一种锰化合物的制备方法，包括同时向锰化合物施加机械力和热能以除去锰化合物颗粒中存在的缺陷并控制颗粒的聚集和聚集的形状的步骤 颗粒，使用通过上述方法制备的锰化合物作为原料制备具有尖晶石结构的锂锰复合氧化物的方法，以及使用具有尖晶石结构的锂锰复合氧化物的锂或锂离子二次电池，其由尖晶石结构 作为阴极活性物质。 使用由锰化合物制备的具有尖晶石结构的锂锰复合氧化物的锂或锂离子二次电池在颗粒内没有缺陷作为正极活性材料具有优异的充电/放电特性和循环性能。

    Semiconductor device with analog capacitor and method of fabricating the same
    10.
    发明申请
    Semiconductor device with analog capacitor and method of fabricating the same 有权
    具有模拟电容器的半导体器件及其制造方法

    公开(公告)号：US20050153575A1

    公开(公告)日：2005-07-14

    申请号：US11077048

    申请日：2005-03-09

    申请人： Ki-Young Lee ,  Sang-Hoon Park

    发明人： Ki-Young Lee ,  Sang-Hoon Park

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L27/08 ,  G02F1/1335

    CPC分类号： H01L21/76834 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76832 ,  H01L27/0805 ,  H01L28/40 ,  Y10S438/957

    摘要： A semiconductor device having an analog capacitor and a method of fabricating the same are disclosed. The semiconductor device includes a bottom plate electrode disposed at a predetermined region of a semiconductor substrate, and an upper plate electrode having a region overlapped with the bottom plate electrode thereon. The upper plate electrode and the bottom plate electrode are formed of a metal compound. A capacitor dielectric layer is interposed between the bottom plate electrode and the upper plate electrode. A bottom electrode plug and an upper electrode plug are connected to the bottom plate electrode and the upper plate electrode through the interlayer dielectric layer.

    摘要翻译： 公开了一种具有模拟电容器的半导体器件及其制造方法。 半导体器件包括设置在半导体衬底的预定区域的底板电极和具有与底板电极重叠的区域的上板电极。 上板电极和底板电极由金属化合物形成。 电容器电介质层介于底板电极和上板电极之间。 底部电极插头和上部电极插头通过层间绝缘层与底板电极和上部电极连接。