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公开(公告)号：US20090114982A1
公开(公告)日：2009-05-07
申请号：US11901172
申请日：2007-09-13
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A disclosed semiconductor device provided with a power MOSFET includes: a semiconductor substrate constituting a drain; a trench formed on a surface of the semiconductor substrate; a gate electrode in the trench; a body diffusion layer on a surface side of the semiconductor substrate, the body diffusion layer being positioned adjacently to the trench and formed shallower than the trench; a source diffusion layer on the surface of the semiconductor substrate; a first interlayer insulating film formed on the gate electrode; and a source electrode film made of a metallic material and formed on the semiconductor substrate. A top surface of the gate electrode and a top surface of the first interlayer insulating film are formed in a recessed manner in the trench relative to the surface of the semiconductor substrate, and a surface portion of the semiconductor substrate for the trench is formed into a tapered shape.
摘要翻译： 设置有功率MOSFET的公开的半导体器件包括：构成漏极的半导体衬底; 形成在所述半导体衬底的表面上的沟槽; 沟槽中的栅电极; 在所述半导体衬底的表面侧上的体扩散层，所述体扩散层与所述沟槽相邻并且形成为比所述沟槽浅; 在半导体衬底的表面上的源极扩散层; 形成在栅电极上的第一层间绝缘膜; 和由金属材料制成并形成在半导体衬底上的源极电极膜。 栅电极的顶表面和第一层间绝缘膜的顶表面相对于半导体衬底的表面以凹陷方式形成在沟槽中，并且用于沟槽的半导体衬底的表面部分形成为 锥形。
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公开(公告)号：US07745877B2
公开(公告)日：2010-06-29
申请号：US11901172
申请日：2007-09-13
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A disclosed semiconductor device provided with a power MOSFET includes: a semiconductor substrate constituting a drain; a trench formed on a surface of the semiconductor substrate; a gate electrode in the trench; a body diffusion layer on a surface side of the semiconductor substrate, the body diffusion layer being positioned adjacently to the trench and formed shallower than the trench; a source diffusion layer on the surface of the semiconductor substrate; a first interlayer insulating film formed on the gate electrode; and a source electrode film made of a metallic material and formed on the semiconductor substrate. A top surface of the gate electrode and a top surface of the first interlayer insulating film are formed in a recessed manner in the trench relative to the surface of the semiconductor substrate, and a surface portion of the semiconductor substrate for the trench is formed into a tapered shape.
摘要翻译： 设置有功率MOSFET的公开的半导体器件包括：构成漏极的半导体衬底; 形成在所述半导体衬底的表面上的沟槽; 沟槽中的栅电极; 在所述半导体衬底的表面侧上的体扩散层，所述体扩散层与所述沟槽相邻并且形成为比所述沟槽浅; 在半导体衬底的表面上的源极扩散层; 形成在栅电极上的第一层间绝缘膜; 和由金属材料制成并形成在半导体衬底上的源极电极膜。 栅电极的顶表面和第一层间绝缘膜的顶表面相对于半导体衬底的表面以凹陷方式形成在沟槽中，并且用于沟槽的半导体衬底的表面部分形成为 锥形。
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3.发明授权公开(公告)号：US07202549B2
公开(公告)日：2007-04-10
申请号：US10848384
申请日：2004-05-19
IPC分类号： H01L29/00
CPC分类号： H01L28/20 , H01L27/0611 , H01L27/0802
摘要： A semiconductor device, a method for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device are disclosed. The semiconductor device includes a substrate section, a resistor formed on the substrate section, a metal pattern formed on the resistor, an oxide pattern formed on the metal pattern, and a protective film covering the resistor, the metal pattern and the oxide pattern. With this structure, the metal pattern sufficiently prevents formation of an oxide film on a surface of the resistor even when dry ashing or dry etching is performed in the manufacturing process.
摘要翻译： 公开了半导体器件，半导体器件的制造方法和包括半导体器件的集成电路。 该半导体装置包括基板部，形成在基板部上的电阻，形成在电阻上的金属图案，形成在金属图案上的氧化物图案，以及覆盖电阻，金属图案和氧化物图案的保护膜。 通过这种结构，即使在制造过程中进行干法灰化或干法蚀刻，金属图案也充分地防止了在电阻器的表面上形成氧化膜。
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公开(公告)号：US20050212085A1
公开(公告)日：2005-09-29
申请号：US11059725
申请日：2005-02-17
IPC分类号： H01L21/3205 , H01L21/02 , H01L21/822 , H01L23/52 , H01L23/522 , H01L23/525 , H01L27/01 , H01L27/04 , H01L29/00
CPC分类号： H01L27/0802 , H01L23/5228 , H01L27/016 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: an insulating film; a metal thin-film resistance element; a wiring pattern formed on the insulating film, a part of which forms an electrode for electrically connecting with the metal thin-film resistance element; and a side wall produced at least on a side surface of the electrode of the wiring pattern, and made of an insulation material, wherein: the metal thin-film resistance element is produced across a top surface of the electrode and a surface of the insulating film via a surface of the side wall.
摘要翻译： 半导体器件包括：绝缘膜; 金属薄膜电阻元件; 形成在所述绝缘膜上的布线图形，其一部分形成用于与所述金属薄膜电阻元件电连接的电极; 以及至少在所述布线图案的电极的侧面上形成的侧壁，并且由绝缘材料制成，其中：所述金属薄膜电阻元件跨越所述电极的顶表面和所述绝缘体的表面 膜通过侧壁的表面。
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5.发明授权公开(公告)号：US07718502B2
公开(公告)日：2010-05-18
申请号：US11984167
申请日：2007-11-14
IPC分类号： H01L29/72
CPC分类号： H01C17/075 , H01C7/006 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor apparatus includes a wiring pattern, an insulating film, and a thin-metal-film resistor element. The insulating film is formed on the wiring pattern having connection holes vertically penetrating there-through to expose part of the wiring pattern at bottom regions of the connection holes. The connection holes are arranged with a space there-between. The thin-metal-film resistor element is formed on the insulating film and extending to continuously overlay and contact surfaces of the insulating film, inner walls of the connection holes, and the wiring pattern at the bottom regions of the connection holes.
摘要翻译： 半导体装置包括布线图案，绝缘膜和薄金属膜电阻元件。 绝缘膜形成在具有垂直贯穿其中的连接孔的布线图案上，以暴露连接孔的底部区域的布线图案的一部分。 连接孔之间具有空间。 金属薄膜电阻元件形成在绝缘膜上并延伸到绝缘膜，连接孔的内壁和连接孔的底部区域的布线图案的连续覆盖和接触。
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公开(公告)号：US07550819B2
公开(公告)日：2009-06-23
申请号：US11061548
申请日：2005-02-18
申请人： Kimihiko Yamashita
发明人： Kimihiko Yamashita
IPC分类号： H01L29/00
CPC分类号： H01L23/5228 , G01R15/04 , H01L21/768 , H01L23/5226 , H01L2924/0002 , Y10T428/24802 , Y10T428/24917 , H01L2924/00
摘要： A semiconductor device having a metal thin-film resistance on an insulation film includes first and second contact holes formed in the insulation film, a first conductive plug formed in the first contact hole, a second conductive plug formed in the second contact hole simultaneously to formation of the first conductive plug, a metal thin-film resistance formed on the first conductive plug and on the insulation film, and a metal interconnection pattern formed on the second conductive plug and the insulation film.
摘要翻译： 在绝缘膜上具有金属薄膜电阻的半导体器件包括形成在绝缘膜中的第一和第二接触孔，形成在第一接触孔中的第一导电插塞，形成在第二接触孔中的第二导电插塞同时形成 形成在第一导电插塞和绝缘膜上的金属薄膜电阻以及形成在第二导电插塞和绝缘膜上的金属互连图案。
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公开(公告)号：US20060027892A1
公开(公告)日：2006-02-09
申请号：US11060753
申请日：2005-08-16
IPC分类号： H01L29/00
CPC分类号： H01L23/5228 , H01L21/76805 , H01L21/76843 , H01L27/0802 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device equipped with a metal thin film resistor is disclosed. The semiconductor device includes a second interlayer insulating film formed on a first interlayer insulating film including a formation area of a wiring pattern. Connecting holes are formed in the second interlayer insulating film corresponding to both ends of the metal thin film resistor and the wiring pattern. An upper part of each connecting hole is formed in a taper shape. A sidewall is formed on the inner wall of each connecting hole. The metal thin film resistor is formed on the second interlayer insulating film between the connecting holes, inside of each connecting hole, and on the wiring pattern.
摘要翻译： 公开了一种配备有金属薄膜电阻器的半导体器件。 半导体器件包括形成在包括布线图案的形成区域的第一层间绝缘膜上的第二层间绝缘膜。 在与金属薄膜电阻器的两端对应的第二层间绝缘膜和布线图案中形成连接孔。 每个连接孔的上部形成为锥形。 在每个连接孔的内壁上形成侧壁。 金属薄膜电阻器形成在第二层间绝缘膜之间的连接孔之间，每个连接孔内部和布线图案之间。
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公开(公告)号：US07999352B2
公开(公告)日：2011-08-16
申请号：US11060753
申请日：2005-02-18
IPC分类号： H01L27/08
CPC分类号： H01L23/5228 , H01L21/76805 , H01L21/76843 , H01L27/0802 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device equipped with a metal thin film resistor is disclosed. The semiconductor device includes a second interlayer insulating film formed on a first interlayer insulating film including a formation area of a wiring pattern. Connecting holes are formed in the second interlayer insulating film corresponding to both ends of the metal thin film resistor and the wiring pattern. An upper part of each connecting hole is formed in a taper shape. A sidewall is formed on the inner wall of each connecting hole. The metal thin film resistor is formed on the second interlayer insulating film between the connecting holes, inside of each connecting hole, and on the wiring pattern.
摘要翻译： 公开了一种配备有金属薄膜电阻器的半导体器件。 半导体器件包括形成在包括布线图案的形成区域的第一层间绝缘膜上的第二层间绝缘膜。 在与金属薄膜电阻器的两端对应的第二层间绝缘膜和布线图案中形成连接孔。 每个连接孔的上部形成为锥形。 在每个连接孔的内壁上形成侧壁。 金属薄膜电阻器形成在第二层间绝缘膜之间的连接孔之间，每个连接孔内部和布线图案之间。
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公开(公告)号：US07986028B2
公开(公告)日：2011-07-26
申请号：US11792471
申请日：2006-09-21
IPC分类号： H01L29/00
CPC分类号： H01L27/016 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, includes a lower layer side insulation film; a wiring pattern formed on the lower layer side insulation film; a base insulation film formed on the lower layer side insulation film and the wiring pattern; and a plurality of metal thin film resistance elements formed on the base insulation film; wherein a connection hole is formed in the base insulation film on the wiring pattern; the wiring pattern and the metal thin film resistance element are electrically connected in the connection hole; the metal thin film resistance element has a belt shape part arranged separately from the connection hole and a connection part continuously formed with the belt shape part and connected to the wiring pattern in the connection hole; and the connection parts of at least two of the metal thin film resistance element are formed in the single connection hole with a gap in between said connection parts.
摘要翻译： 一种半导体器件，包括下层侧绝缘膜; 形成在下层侧绝缘膜上的布线图案; 形成在下层侧绝缘膜和布线图案上的基底绝缘膜; 以及形成在所述基底绝缘膜上的多个金属薄膜电阻元件; 其中在所述布线图案上的所述基底绝缘膜中形成连接孔; 布线图案和金属薄膜电阻元件在连接孔中电连接; 金属薄膜电阻元件具有与连接孔分开布置的带状部分和连续形成带状部分并且连接到连接孔中的布线图案的连接部分; 并且金属薄膜电阻元件中的至少两个的连接部分形成在单个连接孔中，在所述连接部分之间具有间隙。
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10.发明申请公开(公告)号：US20080237799A1
公开(公告)日：2008-10-02
申请号：US12055947
申请日：2008-03-26
申请人： Kimihiko Yamashita
发明人： Kimihiko Yamashita
IPC分类号： H01L29/00
CPC分类号： H01L27/016
摘要： A semiconductor device is provided wherein a foundation insulating film is formed over a semiconductor substrate, a metal resistance element is formed on the foundation insulating film, and contacts are formed at both ends of the metal resistance element in a longitudinal direction of the metal resistance element and connected to the metal resistance element. The foundation insulating film comprises a single upwardly concave curved surface constituting not less than about 40 percent of an upper surface of the metal resistance element between the contacts in the longitudinal direction thereof. The curved surface of the foundation insulating film causes the metal resistance element to comprise a single upwardly concave curved surface constituting not less than about 40 percent of upper and lower surfaces of the metal resistance element between the contacts in the longitudinal direction thereof.
摘要翻译： 提供一种半导体器件，其中在半导体衬底上形成基础绝缘膜，在基础绝缘膜上形成金属电阻元件，并且在金属电阻元件的金属电阻元件的纵向上的两端形成触点 并连接到金属电阻元件。 基础绝缘膜包括单个向上凹的弯曲表面，其构成在其纵向方向上的触点之间不小于金属电阻元件的上表面的大约40％。 基础绝缘膜的弯曲表面使得金属电阻元件包括构成接触件之间的金属电阻元件的纵向方向上的上表面和下表面的大约40％的单个向上凹的曲面。
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