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    Semiconductor device and manufacturing method of the semiconductor device
    1.
    发明授权
    Semiconductor device and manufacturing method of the semiconductor device 有权
    半导体装置及其制造方法

    公开(公告)号：US07834393B2

    公开(公告)日：2010-11-16

    申请号：US11894319

    申请日：2007-08-20

    申请人： Kikuo Saka

    发明人： Kikuo Saka

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7813 ,  H01L27/0207 ,  H01L29/0696 ,  H01L29/4916 ,  H01L29/66734

    摘要： A semiconductor device includes a power MOSFET including a trench formed on a surface of a semiconductor layer forming a drain; a gate electrode formed in the trench via a gate insulation film and made of poly-silicon; a channel diffusion layer formed at a surface side of the semiconductor layer shallower than the trench by neighboring the trench; and a source diffusion layer formed at a surface side of the channel diffusion layer by neighboring the trench; wherein a reverse impurity layer is provided at a bottom part side of the trench of the poly-silicon forming the gate electrode; and an impurity ion that is a conductive type opposite to the conductive type of an impurity ion provided in the poly-silicon at a surface side of the trench is provided in the reverse impurity layer.

    摘要翻译： 半导体器件包括：功率MOSFET，包括形成在形成漏极的半导体层的表面上的沟槽; 栅电极，经由栅极绝缘膜形成在沟槽中并由多晶硅制成; 沟槽扩散层，形成在所述半导体层的表面侧，通过相邻所述沟槽而比所述沟槽浅; 以及源极扩散层，其通过与所述沟槽相邻形成在所述沟道扩散层的表面侧; 其中在形成栅电极的多晶硅的沟槽的底部侧设置反向杂质层; 并且在反向杂质层中设置与在沟槽的表面侧设置在多晶硅中的杂质离子的导电类型相反的导电类型的杂质离子。

    Semiconductor device and manufacturing method of the semiconductor device
    2.
    发明申请
    Semiconductor device and manufacturing method of the semiconductor device 有权
    半导体装置及其制造方法

    公开(公告)号：US20080048254A1

    公开(公告)日：2008-02-28

    申请号：US11894319

    申请日：2007-08-20

    申请人： Kikuo Saka

    发明人： Kikuo Saka

    IPC分类号： H01L29/94 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L27/0207 ,  H01L29/0696 ,  H01L29/4916 ,  H01L29/66734

    摘要： A semiconductor device includes a power MOSFET including a trench formed on a surface of a semiconductor layer forming a drain; a gate electrode formed in the trench via a gate insulation film and made of poly-silicon; a channel diffusion layer formed at a surface side of the semiconductor layer shallower than the trench by neighboring the trench; and a source diffusion layer formed at a surface side of the channel diffusion layer by neighboring the trench; wherein a reverse impurity layer is provided at a bottom part side of the trench of the poly-silicon forming the gate electrode; and an impurity ion that is a conductive type opposite to the conductive type of an impurity ion provided in the poly-silicon at a surface side of the trench is provided in the reverse impurity layer.

    摘要翻译： 半导体器件包括：功率MOSFET，包括形成在形成漏极的半导体层的表面上的沟槽; 栅电极，经由栅极绝缘膜形成在沟槽中并由多晶硅制成; 沟槽扩散层，形成在所述半导体层的表面侧，通过相邻所述沟槽而比所述沟槽浅; 以及源极扩散层，其通过与所述沟槽相邻形成在所述沟道扩散层的表面侧; 其中在形成栅电极的多晶硅的沟槽的底部侧设置反向杂质层; 并且在反向杂质层中设置与在沟槽的表面侧设置在多晶硅中的杂质离子的导电类型相反的导电类型的杂质离子。

    Method of determining the amount of projection exposure
    4.
    发明授权
    Method of determining the amount of projection exposure 失效
    确定投影曝光量的方法

    公开(公告)号：US06156463A

    公开(公告)日：2000-12-05

    申请号：US251843

    申请日：1999-02-17

    申请人： Kikuo Saka

    发明人： Kikuo Saka

    IPC分类号： G03F1/00 ,  G03F1/68 ,  G03F7/20 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  G03F9/00

    CPC分类号： G03F7/70558 ,  G03F1/44

    摘要： A method of determining the amount of exposure is provided, in which a projection exposure is carried out onto a photoresist film using a photomask, having a plurality of openings with transmittance values different from one opening to the next stepwise, and through which light beams are irradiated for the exposure. Subsequently, the openings from which the photoresist is completely removed are observed and a lowest light transmittance value is found among the corresponding openings, to thereby the minimum amount of the exposure E.sub.th for removing the photoresist film is determined. The minimum amount of the projection exposure is found by exposing a plurality of portions with a single exposure step, and the determination of amount of the exposure becomes feasible with relative ease.

    摘要翻译： 提供了一种确定曝光量的方法，其中使用光掩模进行对光致抗蚀剂膜进行投影曝光，其具有多个开口，透光率值不同于一个开口到下一个逐步的开口，并且光束 照射曝光。 随后，观察到光致抗蚀剂完全除去的开口，并且在相应的开口中发现最低的透光率值，从而确定用于除去光致抗蚀剂膜的最小曝光量。 通过用单一曝光步骤曝光多个部分来发现投影曝光的最小量，并且相对容易地确定曝光量变得可行。

    Semiconductor device and manufacturing method thereof
    5.
    发明申请
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US20090114982A1

    公开(公告)日：2009-05-07

    申请号：US11901172

    申请日：2007-09-13

    申请人： Kikuo Saka ,  Kimihiko Yamashita ,  Toshiyuki Takemori ,  Yuji Watanabe

    发明人： Kikuo Saka ,  Kimihiko Yamashita ,  Toshiyuki Takemori ,  Yuji Watanabe

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

    摘要： A disclosed semiconductor device provided with a power MOSFET includes: a semiconductor substrate constituting a drain; a trench formed on a surface of the semiconductor substrate; a gate electrode in the trench; a body diffusion layer on a surface side of the semiconductor substrate, the body diffusion layer being positioned adjacently to the trench and formed shallower than the trench; a source diffusion layer on the surface of the semiconductor substrate; a first interlayer insulating film formed on the gate electrode; and a source electrode film made of a metallic material and formed on the semiconductor substrate. A top surface of the gate electrode and a top surface of the first interlayer insulating film are formed in a recessed manner in the trench relative to the surface of the semiconductor substrate, and a surface portion of the semiconductor substrate for the trench is formed into a tapered shape.

    摘要翻译： 设置有功率MOSFET的公开的半导体器件包括：构成漏极的半导体衬底; 形成在所述半导体衬底的表面上的沟槽; 沟槽中的栅电极; 在所述半导体衬底的表面侧上的体扩散层，所述体扩散层与所述沟槽相邻并且形成为比所述沟槽浅; 在半导体衬底的表面上的源极扩散层; 形成在栅电极上的第一层间绝缘膜; 和由金属材料制成并形成在半导体衬底上的源极电极膜。 栅电极的顶表面和第一层间绝缘膜的顶表面相对于半导体衬底的表面以凹陷方式形成在沟槽中，并且用于沟槽的半导体衬底的表面部分形成为 锥形。

    Semiconductor device and manufacturing method thereof
    6.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US07745877B2

    公开(公告)日：2010-06-29

    申请号：US11901172

    申请日：2007-09-13

    申请人： Kikuo Saka ,  Kimihiko Yamashita ,  Toshiyuki Takemori ,  Yuji Watanabe

    发明人： Kikuo Saka ,  Kimihiko Yamashita ,  Toshiyuki Takemori ,  Yuji Watanabe

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

    摘要： A disclosed semiconductor device provided with a power MOSFET includes: a semiconductor substrate constituting a drain; a trench formed on a surface of the semiconductor substrate; a gate electrode in the trench; a body diffusion layer on a surface side of the semiconductor substrate, the body diffusion layer being positioned adjacently to the trench and formed shallower than the trench; a source diffusion layer on the surface of the semiconductor substrate; a first interlayer insulating film formed on the gate electrode; and a source electrode film made of a metallic material and formed on the semiconductor substrate. A top surface of the gate electrode and a top surface of the first interlayer insulating film are formed in a recessed manner in the trench relative to the surface of the semiconductor substrate, and a surface portion of the semiconductor substrate for the trench is formed into a tapered shape.

    摘要翻译： 设置有功率MOSFET的公开的半导体器件包括：构成漏极的半导体衬底; 形成在所述半导体衬底的表面上的沟槽; 沟槽中的栅电极; 在所述半导体衬底的表面侧上的体扩散层，所述体扩散层与所述沟槽相邻并且形成为比所述沟槽浅; 在半导体衬底的表面上的源极扩散层; 形成在栅电极上的第一层间绝缘膜; 和由金属材料制成并形成在半导体衬底上的源极电极膜。 栅电极的顶表面和第一层间绝缘膜的顶表面相对于半导体衬底的表面以凹陷方式形成在沟槽中，并且用于沟槽的半导体衬底的表面部分形成为 锥形。