公开(公告)号：US20240428868A1

公开(公告)日：2024-12-26

申请号：US18747270

申请日：2024-06-18

Applicant: Kioxia Corporation

Inventor： Naoto KUMANO ,  Kenji SAKURADA

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/20

Abstract: A memory system includes a semiconductor memory including a plurality of first memory cells each configured to store data in a non-volatile manner according to a threshold voltage, and a controller. The controller is configured to perform a first error correction process for the plurality of first memory cells, based on first hard bit data and first soft bit data acquired using a plurality of first soft bit voltages that have been calculated based on a shift voltage, and to correct the shift voltage when a condition based on correction data generated during the first error correction process, is satisfied.

公开(公告)号：US20240319908A1

公开(公告)日：2024-09-26

申请号：US18590789

申请日：2024-02-28

Applicant: Kioxia Corporation

Inventor： Yousuke KINO ,  Ryo NOGAMI ,  Atsushi TAKAYAMA ,  Kenji SAKURADA ,  Naoto KUMANO

IPC: G06F3/06 ,  G06F7/58

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F7/58

Abstract: A memory circuit includes a plurality of storage areas each designated by one of a plurality of addresses. The control circuit stores a plurality of values, all of which are different from each other, in the plurality of storage areas, generates a first random number, obtains a first address that is one of the plurality of addresses using the first random number, reads a first value stored in a first storage area designated by the first address, and reads a second value stored in a second storage area designated by a second address. The second address is an address having the largest value among a range of addresses from which the first address can be obtained. The control circuit writes the second value into the first storage area after reading the first value therefrom. The control circuit outputs the first value as one value of an output random number.

公开(公告)号：US20230298685A1

公开(公告)日：2023-09-21

申请号：US17896887

申请日：2022-08-26

Applicant: KIOXIA CORPORATION

Inventor： Motoki SHIMIZU ,  Kenji SAKURADA ,  Naoto KUMANO

IPC: G11C29/52 ,  G11C29/02 ,  G11C8/08 ,  H03M13/11

CPC classification number: G11C29/52 ,  G11C29/021 ,  G11C8/08 ,  H03M13/1125

Abstract: A memory system includes a semiconductor memory device including a plurality of memory cells each configured to store data in a non-volatile manner according to a threshold voltage thereof and connected to a word line, and a controller configured to perform an error correction based on hard bit data and soft bit data read from the plurality of memory cells, generate a first table based on corrected data, determine a voltage difference between a first voltage and a second voltage, the first voltage being a voltage applied to the word line when the data being corrected is read, and correct the first table based on the voltage difference.

公开(公告)号：US20250157564A1

公开(公告)日：2025-05-15

申请号：US19021029

申请日：2025-01-14

Applicant: Kioxia Corporation

Inventor： Motoki SHIMIZU ,  Kenji SAKURADA ,  Naoto KUMANO

IPC: G11C29/52 ,  G11C8/08 ,  G11C29/02 ,  H03M13/11

Abstract: A memory system includes a semiconductor memory device including a plurality of memory cells each configured to store data in a non-volatile manner according to a threshold voltage thereof and connected to a word line, and a controller configured to perform an error correction based on hard bit data and soft bit data read from the plurality of memory cells, generate a first table based on corrected data, determine a voltage difference between a first voltage and a second voltage, the first voltage being a voltage applied to the word line when the data being corrected is read, and correct the first table based on the voltage difference.

公开(公告)号：US20230088099A1

公开(公告)日：2023-03-23

申请号：US18053271

申请日：2022-11-07

Applicant: Kioxia Corporation

Inventor： Kenji SAKURADA ,  Naomi TAKEDA ,  Masanobu SHIRAKAWA ,  Marie TAKADA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G06F3/06 ,  G11C16/34

Abstract: A memory system includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.

公开(公告)号：US20230045340A1

公开(公告)日：2023-02-09

申请号：US17589365

申请日：2022-01-31

Applicant: Kioxia Corporation

Inventor： Naoto KUMANO ,  Kenji SAKURADA

IPC: G11C16/26 ,  G11C16/04 ,  G06F11/10

Abstract: According to one embodiment, a memory system includes first and second memory cells and a controller. The controller obtains first and second data based on a first read operation from the first and second memory cells, respectively. The controller obtains third and fourth data based on a second read from the first and second memory cells, respectively. The second read operation is different from the first read operation in a read voltage. The controller sets first and second values indicating likelihood of data stored in the first and second memory cells, respectively, based on information indicating locations of the first and second memory cells. The controller performs error correction on data read from the first and second memory cells using at least the third data and the first value, and using at least fourth data and the second value, respectively.

公开(公告)号：US20210375372A1

公开(公告)日：2021-12-02

申请号：US17117937

申请日：2020-12-10

Applicant: Kioxia Corporation

Inventor： Kenji SAKURADA ,  Naomi TAKEDA ,  Masanobu SHIRAKAWA ,  Marie TAKADA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G06F3/06

Abstract: A memory system in an embodiment includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.

公开(公告)号：US20210211142A1

公开(公告)日：2021-07-08

申请号：US17020397

申请日：2020-09-14

Applicant: Kioxia Corporation

Inventor： Kuminori HYODO ,  Kenji SAKURADA ,  Yasuhiko KUROSAWA ,  Takashi NAKAGAWA

IPC: H03M13/11 ,  H03M13/45 ,  H03M13/00

Abstract: According to one embodiment, a decoding device comprises a converter configured to convert read data to first likelihood information by using a first conversion table, a decoder which decodes the first likelihood information, a controller which outputs a decoding result of the decoder when the decoder succeeds decoding, and a creator module which creates a second conversion table based on the decoding result when the decoder fails decoding. When the second conversion table is created, at least a part of the decoding result is converted to second likelihood information by using the second conversion table the second likelihood information is decoded.