公开(公告)号：US12087396B2

公开(公告)日：2024-09-10

申请号：US17898981

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Takehisa Kurosawa ,  Akio Sugahara ,  Mitsuhiro Abe ,  Hisashi Fujikawa ,  Yuji Nagai ,  Zhao Lu

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/20

CPC classification number: G11C7/222 ,  G11C7/1069 ,  G11C7/20

Abstract: A memory system includes a memory controller and a semiconductor storage device including a power supply pad, first, second, third, and fourth signal pads to which first, second, third, and fourth signals are respectively input, a memory cell array, a data register, and a control circuit executing an operation to output data stored in the data register through the fourth signal pad. The memory controller performs a mode setting operation by toggling the third signal input, after at least the first or second signal has been switched at a first timing after supplying power to the power supply pad, perform an initial setting operation by transmitting a power-on read command at a second timing after the first timing, and transmit a data-out command, at a third timing after the second timing. The semiconductor storage device receives the power-on read and data-out commands via the first and second signal pads.

公开(公告)号：US11507316B2

公开(公告)日：2022-11-22

申请号：US17091005

申请日：2020-11-06

Applicant: Kioxia Corporation

Inventor： Akio Sugahara ,  Yuji Nagai

IPC: G06F3/06 ,  G06F12/06 ,  G11C16/06 ,  G06F12/02 ,  G11C7/10 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26

Abstract: A memory device includes a memory cell array configured to store data, a control circuit configured to control the memory cell array in response to a command; and a receiver configured to be placed in an active state based on a first signal, a second signal, or an operation result of an address and the command, and be enabled to receive a command or data.

公开(公告)号：US12229450B2

公开(公告)日：2025-02-18

申请号：US18524477

申请日：2023-11-30

Applicant: KIOXIA CORPORATION

Inventor： Akio Sugahara ,  Zhao Lu ,  Takehisa Kurosawa ,  Yuji Nagai

IPC: G11C7/00 ,  G06F3/06 ,  G11C16/04 ,  G11C16/26

Abstract: A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.

公开(公告)号：US11923020B2

公开(公告)日：2024-03-05

申请号：US17679667

申请日：2022-02-24

Applicant: Kioxia Corporation

Inventor： Hiroyuki Ishii ,  Yuji Nagai ,  Makoto Miakashi ,  Tomoko Kajiyama ,  Hayato Konno

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

Abstract: A memory device includes a plurality of memory cell transistors, a first word line, a controller, and a storage circuit. Each of the plurality of memory cell transistors stores a plurality of pieces of bit data. The first word line is connected to a plurality of first memory cell transistors in the plurality of memory cell transistors. The controller performs a loop process including repetition of a program loop including a program operation and a first verification operation. The storage circuit stores status information. The controller performs the loop process, then performs a second verification operation, and stores first status data corresponding to a result of the loop process and second status data corresponding to a result of the second verification operation in the storage circuit, in a write operation using the plurality of first memory cell transistors as targets.

公开(公告)号：US12062412B2

公开(公告)日：2024-08-13

申请号：US17806965

申请日：2022-06-15

Applicant: KIOXIA CORPORATION

Inventor： Zhao Lu ,  Yuji Nagai ,  Akio Sugahara ,  Takehisa Kurosawa ,  Masaru Koyanagi

IPC: G11C7/22 ,  G11C7/08 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/08 ,  G11C7/1063 ,  G11C7/109

Abstract: A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.

公开(公告)号：US11942180B2

公开(公告)日：2024-03-26

申请号：US17809114

申请日：2022-06-27

Applicant: KIOXIA CORPORATION

Inventor： Zhao Lyu ,  Akio Sugahara ,  Takehisa Kurosawa ,  Yuji Nagai ,  Hisashi Fujikawa

IPC: G11C7/10 ,  G11C8/06

CPC classification number: G11C7/1063 ,  G11C7/1039 ,  G11C7/109 ,  G11C8/06

Abstract: A memory system includes semiconductor memory devices and a control device. Each of the semiconductor memory devices includes a first pad to which a first signal is input, a second pad to which a second signal is input, a third pad to which a third signal is input, a memory cell array, a sense amplifier, and a data register. In a first mode, after the first signal is switched, a command set instructing a data out operation is input via the second pad. In a second mode, after the first signal is switched, the command is input via at least the third pad. The control device executes a first operation assigning different addresses to the respective semiconductor memory devices and a second operation causing the modes of the respective semiconductor memory devices to be switched from the first to the second mode.

公开(公告)号：US11322480B2

公开(公告)日：2022-05-03

申请号：US16523587

申请日：2019-07-26

Applicant: KIOXIA CORPORATION

Inventor： Toshihiro Suzuki ,  Yuji Nagai

IPC: G06F13/00 ,  H01L25/065 ,  H01L25/10 ,  G06F13/16 ,  G11C5/04 ,  G06F13/40 ,  G06F13/42 ,  G11C7/10 ,  G11C5/06 ,  G11C16/20 ,  G11C16/04 ,  H03K19/20 ,  G11C16/10 ,  G11C16/26 ,  G11C7/20

Abstract: A semiconductor memory device includes a substrate that has a first main surface and a second main surface opposite to the first main surface, a first semiconductor chip which is mounted on the first main surface and includes a first register, a plurality of first input/output (IO) terminals, and a first circuit connected between the first IO terminals and the first register, and a second semiconductor chip which is mounted on the second main surface and includes a second register, a plurality of second input/output (IO) terminals, and a second circuit connected between the second IO terminals and the second register. The second circuit is connected to the second IO terminals through input lines and to the second register through output lines, and is configured to change a connection path between the input lines and the output lines in response to a connection change command.

公开(公告)号：US11715535B2

公开(公告)日：2023-08-01

申请号：US17181660

申请日：2021-02-22

Applicant: KIOXIA CORPORATION

Inventor： Yoshikazu Harada ,  Yuji Nagai ,  Kenro Kikuchi

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C7/04 ,  G11C16/08 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C7/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor storage device includes a memory cell connected to a word line, and a control circuit configured to execute a write operation that repeats a program loop including a program operation of applying a program voltage to the word line and a verification operation to be executed after the program operation. The control circuit, during the write operation, increases the program voltage by a first amount each time the program loop is repeated, and after the write operation is interrupted and resumed, changes the increase in the program voltage from the first amount to a second amount, which is a positive number smaller than the first amount.

公开(公告)号：US12001723B2

公开(公告)日：2024-06-04

申请号：US17967909

申请日：2022-10-18

Applicant: Kioxia Corporation

Inventor： Akio Sugahara ,  Yuji Nagai

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G11C7/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G06F12/0246 ,  G06F12/06 ,  G11C7/1063 ,  G11C7/109 ,  G11C16/06 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a memory cell array configured to store data, a data input and output interface configured to receive a command, an address, and data to be written into the memory cell array from the memory controller, and to output data read from the memory cell array to the memory controller, and a control circuit configured to control the memory cell array to perform an operation in response to receipt of a command while a first control signal is being asserted by the memory controller and receipt of an address subsequent to the command while a second control signal is being asserted by the memory controller.

公开(公告)号：US11861226B2

公开(公告)日：2024-01-02

申请号：US17464791

申请日：2021-09-02

Applicant: Kioxia Corporation

Inventor： Akio Sugahara ,  Zhao Lu ,  Takehisa Kurosawa ,  Yuji Nagai

IPC: G11C7/00 ,  G06F3/06 ,  G11C16/04 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/26

Abstract: A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.