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    Silicon controlled rectifier structure with improved junction breakdown and leakage control
    1.
    发明授权
    Silicon controlled rectifier structure with improved junction breakdown and leakage control 有权
    可控硅整流器结构，具有改进的结击穿和泄漏控制

    公开(公告)号：US08692290B2

    公开(公告)日：2014-04-08

    申请号：US13226838

    申请日：2011-09-07

    申请人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Alain Loiseau

    发明人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Alain Loiseau

    IPC分类号： H01L29/73 ,  H01L21/331 ,  G06F17/50

    CPC分类号： H01L29/66363 ,  G06F17/50 ,  H01L27/0262 ,  H01L29/74 ,  H01L29/7436 ,  H02H9/04

    摘要： Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.

    摘要翻译： 可控硅整流器的器件结构和设计结构，以及制造可控硅整流器的方法。 器件结构包括设置在包含可控硅整流器的第一和第二p-n结的器件区域的顶表面上的不同材料的第一和第二层。 第一层横向定位在与第一p-n结垂直对准的顶表面上。 第二层横向定位在与第二p-n结垂直对准的器件区域的顶表面上。 包括第二层的材料具有比包含第一层的材料更高的电阻率。

    SILICON CONTROLLED RECTIFIER STRUCTURE WITH IMPROVED JUNCTION BREAKDOWN AND LEAKAGE CONTROL
    2.
    发明申请
    SILICON CONTROLLED RECTIFIER STRUCTURE WITH IMPROVED JUNCTION BREAKDOWN AND LEAKAGE CONTROL 有权
    硅控制整流器结构具有改进的断路和漏电控制

    公开(公告)号：US20130057991A1

    公开(公告)日：2013-03-07

    申请号：US13226838

    申请日：2011-09-07

    申请人： Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Alain Loiseau

    发明人： Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Alain Loiseau

    IPC分类号： H02H9/04 ,  H01L21/332 ,  G06F17/50 ,  H01L29/74

    CPC分类号： H01L29/66363 ,  G06F17/50 ,  H01L27/0262 ,  H01L29/74 ,  H01L29/7436 ,  H02H9/04

    摘要： Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.

    摘要翻译： 可控硅整流器的器件结构和设计结构，以及制造可控硅整流器的方法。 器件结构包括设置在包含可控硅整流器的第一和第二p-n结的器件区域的顶表面上的不同材料的第一和第二层。 第一层横向定位在与第一p-n结垂直对准的顶表面上。 第二层横向定位在与第二p-n结垂直对准的器件区域的顶表面上。 包括第二层的材料具有比包含第一层的材料更高的电阻率。

    ESD FIELD-EFFECT TRANSISTOR AND INTEGRATED DIFFUSION RESISTOR
    5.
    发明申请
    ESD FIELD-EFFECT TRANSISTOR AND INTEGRATED DIFFUSION RESISTOR 有权
    ESD场效应晶体管和集成扩散电阻

    公开(公告)号：US20130020645A1

    公开(公告)日：2013-01-24

    申请号：US13188094

    申请日：2011-07-21

    申请人： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Rahul Mishra ,  Junjun Li ,  Mujahid Muhammad

    发明人： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Rahul Mishra ,  Junjun Li ,  Mujahid Muhammad

    IPC分类号： H01L29/772 ,  G06F9/45 ,  H01L21/336

    CPC分类号： H01L29/41775 ,  H01L27/0266 ,  H01L29/1087 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.

    摘要翻译： 静电放电保护装置，静电放电保护装置的制造方法以及静电放电保护装置的设计结构。 第一场效应晶体管的漏极和较高电阻的扩散电阻可以形成为掺杂区域的不同部分。 可以使用布置在掺杂区域中的介电材料的隔离区域和选择性硅化物形成来限定与第一场效应晶体管的漏极直接耦合的扩散电阻器。 静电放电保护器件还可以包括第二场效应晶体管，其具有作为与扩散电阻器直接耦合并且由扩散电阻器与第一场效应晶体管的漏极间接耦合的掺杂区域的一部分的漏极。

    SCR/MOS clamp for ESD protection of integrated circuits
    6.
    发明授权
    SCR/MOS clamp for ESD protection of integrated circuits 失效
    用于集成电路ESD保护的SCR / MOS钳位

    公开(公告)号：US08354722B2

    公开(公告)日：2013-01-15

    申请号：US13149174

    申请日：2011-05-31

    申请人： John B. Campi, Jr. ,  Shunhua Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    发明人： John B. Campi, Jr. ,  Shunhua Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    IPC分类号： H01L29/78 ,  H01L29/788 ,  H02H9/00

    CPC分类号： H01L29/742 ,  H01L27/0262

    摘要： An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.

    摘要翻译： 静电放电（ESD）保护电路，制造ESD保护电路的方法，提供ESD保护的方法以及ESD保护电路的设计结构。 可以在p阱中形成NFET，并且可以在n阱中形成PFET。 在p阱和n阱之间形成的对接p-n结导致形成与NFET和PFET集成的SCR的NPNP结构。 NFET，PFET和SCR被配置为共同保护诸如电源板的焊盘免受ESD事件的影响。 在正常工作期间，NFET，PFET和SCR被RC触发电路偏置，使得ESD保护电路处于高阻抗状态。 在芯片无电源时的ESD事件期间，RC触发电路输出触发信号，使SCR，NFET和PFET进入导通状态，并协同地将ESD电流从受保护的焊盘分流。

    SCR/MOS CLAMP FOR ESD PROTECTION OF INTEGRATED CIRCUITS
    7.
    发明申请
    SCR/MOS CLAMP FOR ESD PROTECTION OF INTEGRATED CIRCUITS 失效
    用于ESD保护集成电路的SCR / MOS钳位

    公开(公告)号：US20120305984A1

    公开(公告)日：2012-12-06

    申请号：US13149174

    申请日：2011-05-31

    申请人： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    发明人： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    IPC分类号： H01L29/747 ,  G06F17/50 ,  H01L21/332

    CPC分类号： H01L29/742 ,  H01L27/0262

    摘要： An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.

    摘要翻译： 静电放电（ESD）保护电路，制造ESD保护电路的方法，提供ESD保护的方法以及ESD保护电路的设计结构。 可以在p阱中形成NFET，并且可以在n阱中形成PFET。 在p阱和n阱之间形成的对接p-n结导致形成与NFET和PFET集成的SCR的NPNP结构。 NFET，PFET和SCR被配置为共同保护诸如电源板的焊盘免受ESD事件的影响。 在正常工作期间，NFET，PFET和SCR被RC触发电路偏置，使得ESD保护电路处于高阻抗状态。 在芯片无电源时的ESD事件期间，RC触发电路输出触发信号，使SCR，NFET和PFET进入导通状态，并协同地将ESD电流从受保护的焊盘分流。

    Electrical overstress protection circuit
    8.
    发明授权
    Electrical overstress protection circuit 有权
    电气过载保护电路

    公开(公告)号：US08363367B2

    公开(公告)日：2013-01-29

    申请号：US12632015

    申请日：2009-12-07

    申请人： John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Mujahid Muhammad

    发明人： John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Mujahid Muhammad

    IPC分类号： H02H9/00

    CPC分类号： H01L27/0251 ,  G06F17/5045

    摘要： A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond.

    摘要翻译： 提供了一种用于电力过应力（EOS）保护的半导体电路。 半导体电路采用静电放电（ESD）保护电路，其具有连接到放电电容器的电阻 - 电容（RC）延时网络。 连接具有电压骤回特性或二极管行为的电子部件，以改变在EOS事件下放电晶体管的栅极的逻辑状态。 特别地，电子部件被配置成在电应力（EOS）条件以及ESD事件的整个持续时间期间打开放电电容器的栅极。 可以采用设计结构来设计或制造半导体电路，该半导体电路在没有时间限制的情况下提供针对EOS状态的保护，即不受时间长度超过1微秒的EOS事件的RC时间延迟网络的时间常数的限制。