公开(公告)号：US4926235A

公开(公告)日：1990-05-15

申请号：US106861

申请日：1987-10-13

申请人： Yoichi Tamaki ,  Tokuo Kure ,  Tohru Nakamura ,  Tetsuya Hayashida ,  Kiyoji Ikeda ,  Katsuyoshi Washio ,  Takahiro Onai ,  Akihisa Uchida ,  Kunihiko Watanabe

发明人： Yoichi Tamaki ,  Tokuo Kure ,  Tohru Nakamura ,  Tetsuya Hayashida ,  Kiyoji Ikeda ,  Katsuyoshi Washio ,  Takahiro Onai ,  Akihisa Uchida ,  Kunihiko Watanabe

IPC分类号： H01L21/285 ,  H01L21/763 ,  H01L29/423

CPC分类号： H01L21/763 ,  H01L21/28525 ,  H01L29/42304

摘要： A semiconductor device is disclosed, which includes bipolar transistor each having an emitter, base and collector formed inside each protruding portion of a semiconductor substrate, and trenches for device isolation. The bipolar transistor and the trench are spaced apart from each other by a predetermined spacing. According to this arrangement, the width of a base contact becomes uniform and any change of transistor characteristics can be prevented effectively.

摘要翻译： 公开了一种半导体器件，其包括双极晶体管，每个双极晶体管具有形成在半导体衬底的每个突出部分内的发射极，基极和集电极以及用于器件隔离的沟槽。 双极晶体管和沟槽彼此隔开预定间隔。 根据这种布置，基极接触的宽度变得均匀，并且可以有效地防止晶体管特性的任何变化。

公开(公告)号：US4243506A

公开(公告)日：1981-01-06

申请号：US69058

申请日：1979-08-23

申请人： Kiyoji Ikeda ,  Tetsuya Hayashida

发明人： Kiyoji Ikeda ,  Tetsuya Hayashida

IPC分类号： C23F4/00 ,  H01J37/32 ,  B01K1/00

CPC分类号： H01J37/32082 ,  H01J37/32541 ,  H01J2237/334

摘要： A "planar" type plasma-etching apparatus wherein one electrode is a metallic mesh electrode, while the other electrode is a metallic plate electrode, and wherein a work piece is placed outside the mesh electrode. This apparatus has the advantage that a work piece having a large area can be etched uniformly over its whole surface.

摘要翻译： “平面”型等离子体蚀刻装置，其中一个电极是金属网状电极，而另一个电极是金属板电极，并且其中工件放置在网状电极的外部。 该装置的优点是可以在其整个表面上均匀地蚀刻具有大面积的工件。

公开(公告)号：US5109263A

公开(公告)日：1992-04-28

申请号：US556365

申请日：1990-07-24

申请人： Mitsuo Nanba ,  Tohru Nakamura ,  Kazuo Nakazato ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

发明人： Mitsuo Nanba ,  Tohru Nakamura ,  Kazuo Nakazato ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

IPC分类号： H01L21/331 ,  H01L21/762 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/76229 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/732

摘要： A vertical bipolar transistor arrangement in which the distance between the emitter and the isolation region is kept within a range determined by the sum of emitter depth and base width (i.e., the thickness of the base in the depth direction). This keeps the carriers given by the emitter from getting trapped inside, thereby preventing the cut-off frequency from dropping.

摘要翻译： 发射极和隔离区域之间的距离保持在由发射极深度和基底宽度（即，基底在深度方向上的厚度）确定的范围内的垂直双极晶体管布置。 这样可以防止发射器的载波被捕获到内部，从而防止截止频率的下降。

公开(公告)号：US4949162A

公开(公告)日：1990-08-14

申请号：US201928

申请日：1988-06-03

申请人： Yoichi Tamaki ,  Kiyoji Ikeda ,  Toru Nakamura ,  Akihisa Uchida ,  Toru Koizumi ,  Hiromichi Enami ,  Satoru Isomura ,  Shinji Nakajima ,  Katsumi Ogiue ,  Kaoru Ohgaya

发明人： Yoichi Tamaki ,  Kiyoji Ikeda ,  Toru Nakamura ,  Akihisa Uchida ,  Toru Koizumi ,  Hiromichi Enami ,  Satoru Isomura ,  Shinji Nakajima ,  Katsumi Ogiue ,  Kaoru Ohgaya

IPC分类号： H01L23/485 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L24/02 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/05042 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/3025

摘要： A multilayer semiconductor integrated circuit having a plurality of wiring layers in which at least the lines of a lower layer are extended on wiring channel regions arranged in a grid. Dummy pedestals are formed of the same conductive layer as that forming the lines of the lower layer and are arranged in the intersecting areas of the wiring channel regions where none of the lines of the lower layer is placed. A method of manufacturing such a semiconductor integrated circuit comprises steps of preparing dummy pedestal layout data for arranging the dummy pedestals in all the intersecting areas of the wiring channel regions and line layout data for forming the lines of the lower layer on predetermined wiring channels among all the wiring channel regions, and combining the dummy pedestal layout data and the line layout data by logical sum (OR).

摘要翻译： 一种多层半导体集成电路，其具有多个布线层，其中至少在布置在栅格中的布线沟道区上的下层的布线延伸。 虚拟基座由与形成下层的线相同的导电层形成，并且布置在布线沟道区域的相交区域中，其中没有放置下层的线。 一种制造这样的半导体集成电路的方法包括以下步骤：制备用于在布线沟道区域的所有交叉区域中布置虚设基座的虚拟基座布局数据和用于在预定布线通道上形成下层的线的线路布局数据 布线通道区域，并且通过逻辑和（OR）组合虚拟基座布局数据和线路布局数据。

公开(公告)号：US4829361A

公开(公告)日：1989-05-09

申请号：US120921

申请日：1987-11-16

申请人： Kazuhiko Sagara ,  Tohru Nakamura ,  Kazuo Nakazato ,  Tokuo Kure ,  Kiyoji Ikeda ,  Noriyuki Homma

发明人： Kazuhiko Sagara ,  Tohru Nakamura ,  Kazuo Nakazato ,  Tokuo Kure ,  Kiyoji Ikeda ,  Noriyuki Homma

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8229 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/10 ,  H01L27/102 ,  H01L29/732

CPC分类号： H01L27/1025 ,  H01L21/74 ,  H01L21/762 ,  Y10S257/906

摘要： A semiconductor device wherein a layer doped with impurities is provided between a buried layer and an epitaxial layer, said layer doped with impurities having a conductivity of the type opposite to that of said buried layer and said epitaxial layer, a reversely biasing voltage is applied across the buried layer and the layer doped with impurities, and side surfaces of the epitaxial layer are surrounded by an insulator.This helps effectively prevent the element formed in the epitaxial layer from being affected by .alpha.-particles and greatly improve reliability of the semiconductor device.

摘要翻译： 一种半导体器件，其中在掩埋层和外延层之间提供掺杂有杂质的层，所述层掺杂有与所述掩埋层和所述外延层的导电类型相反的导电类型的杂质，施加反向偏置电压 掺杂有杂质的掩埋层和层，外延层的侧表面被绝缘体包围。 这有助于有效地防止外延层中形成的元件受到α-粒子的影响，并且极大地提高了半导体器件的可靠性。

公开(公告)号：US5237200A

公开(公告)日：1993-08-17

申请号：US833759

申请日：1992-02-11

申请人： Mitsuo Nanba ,  Tohru Nakamura ,  Nakazato Kazuo ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

发明人： Mitsuo Nanba ,  Tohru Nakamura ,  Nakazato Kazuo ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/762 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/76229 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/732

摘要： A vertical bipolar transistor arrangement in which the distance between the emitter and the isolation region is kept within a range determined by the sum of emitter depth and base width (i.e., the thickness of the base in the depth direction). This keeps the carriers given by the emitter from getting trapped inside, thereby preventing the cut-off frequency from dropping.

摘要翻译： 发射极和隔离区域之间的距离保持在由发射极深度和基底宽度（即，基底在深度方向上的厚度）确定的范围内的垂直双极晶体管布置。 这样可以防止发射器的载波被捕获到内部，从而防止截止频率的下降。