公开(公告)号：US4829361A

公开(公告)日：1989-05-09

申请号：US120921

申请日：1987-11-16

申请人： Kazuhiko Sagara ,  Tohru Nakamura ,  Kazuo Nakazato ,  Tokuo Kure ,  Kiyoji Ikeda ,  Noriyuki Homma

发明人： Kazuhiko Sagara ,  Tohru Nakamura ,  Kazuo Nakazato ,  Tokuo Kure ,  Kiyoji Ikeda ,  Noriyuki Homma

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8229 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/10 ,  H01L27/102 ,  H01L29/732

CPC分类号： H01L27/1025 ,  H01L21/74 ,  H01L21/762 ,  Y10S257/906

摘要： A semiconductor device wherein a layer doped with impurities is provided between a buried layer and an epitaxial layer, said layer doped with impurities having a conductivity of the type opposite to that of said buried layer and said epitaxial layer, a reversely biasing voltage is applied across the buried layer and the layer doped with impurities, and side surfaces of the epitaxial layer are surrounded by an insulator.This helps effectively prevent the element formed in the epitaxial layer from being affected by .alpha.-particles and greatly improve reliability of the semiconductor device.

摘要翻译： 一种半导体器件，其中在掩埋层和外延层之间提供掺杂有杂质的层，所述层掺杂有与所述掩埋层和所述外延层的导电类型相反的导电类型的杂质，施加反向偏置电压 掺杂有杂质的掩埋层和层，外延层的侧表面被绝缘体包围。 这有助于有效地防止外延层中形成的元件受到α-粒子的影响，并且极大地提高了半导体器件的可靠性。

公开(公告)号：US4812894A

公开(公告)日：1989-03-14

申请号：US191761

申请日：1988-05-03

申请人： Tohru Nakamura ,  Kazuo Nakazato ,  Noriyuki Homma ,  Kazuhiko Sagara ,  Takeo Shiba ,  Tokuo Kure ,  Tetsuya Hayashida

发明人： Tohru Nakamura ,  Kazuo Nakazato ,  Noriyuki Homma ,  Kazuhiko Sagara ,  Takeo Shiba ,  Tokuo Kure ,  Tetsuya Hayashida

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/337 ,  H01L21/822 ,  H01L23/485 ,  H01L27/04 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/41 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732 ,  H01L29/808 ,  H01L29/06

CPC分类号： H01L29/66272 ,  H01L23/485 ,  H01L27/0658 ,  H01L29/0804 ,  H01L29/0808 ,  H01L29/1004 ,  H01L29/41 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/42316 ,  H01L29/8083 ,  H01L2924/0002

摘要： A semiconductor device includes a first insulation film formed on a monocrystalline substrate and having an opening, a monocrystalline semiconductor layer formed so as to protrude into the first insulation film, and a conductive layer formed in contact with the side section of the monocrystalline semiconductor layer and extending over a second insulation film formed on the monocrystalline semiconductor layer.

摘要翻译： 半导体器件包括形成在单晶衬底上并具有开口的第一绝缘膜，形成为突出到第一绝缘膜中的单晶半导体层和与单晶半导体层的侧部接触形成的导电层，以及 在形成在单晶半导体层上的第二绝缘膜上延伸。

公开(公告)号：US4858184A

公开(公告)日：1989-08-15

申请号：US42698

申请日：1987-04-27

申请人： Noriyuki Homma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

发明人： Noriyuki Homma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

IPC分类号： G11C11/411

CPC分类号： G11C11/4113 ,  G11C11/4116

摘要： A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are inverted and the load device thereof has shielding means for shielding the flip flop from the noise produced within the substrate. Bipolar transistors and Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in a region where the device is provided, and a reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.

摘要翻译： 提供了具有对由α射线引起的软误差具有高免疫性的结构的双极记忆。 触发器的晶体管，即存储器单元的基本电路被反转，并且其负载装置具有屏蔽装置，用于屏蔽触发器与衬底内产生的噪声。 采用双极晶体管和肖特基势垒二极管作为负载器件。 在设置器件的区域中形成掩埋层（通常为n型层）和反向导电型（通常为p型）的掺杂层，并且跨越掩埋层施加反向偏压，并且掺杂 以切断衬底内产生的噪音。

公开(公告)号：US4958320A

公开(公告)日：1990-09-18

申请号：US361633

申请日：1989-06-02

申请人： Noriyuki Homma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

发明人： Noriyuki Homma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

IPC分类号： G11C11/411 ,  H01L27/102

CPC分类号： G11C11/4113 ,  G11C11/4116 ,  H01L27/1025

摘要： A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are inverted and the load device thereof has shielding means for shielding the flip flop from the noise produced within the substrate. Bipolar transistors and Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in a region where the device is provided, and a reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.

摘要翻译： 提供了具有对由α射线引起的软误差具有高免疫性的结构的双极记忆。 触发器的晶体管，即存储器单元的基本电路被反转，并且其负载装置具有屏蔽装置，用于屏蔽触发器与衬底内产生的噪声。 采用双极晶体管和肖特基势垒二极管作为负载器件。 在设置器件的区域中形成掩埋层（通常为n型层）和反向导电型（通常为p型）的掺杂层，并且跨越掩埋层施加反向偏压，并且掺杂 以切断衬底内产生的噪音。

公开(公告)号：US4825281A

公开(公告)日：1989-04-25

申请号：US435552

申请日：1982-10-21

申请人： Kazuo Nakazato ,  Tohru Nakamura ,  Masatoshi Matsuda ,  Takao Miyazaki ,  Tokuo Kure ,  Takahiro Okabe ,  Minoru Nagata

发明人： Kazuo Nakazato ,  Tohru Nakamura ,  Masatoshi Matsuda ,  Takao Miyazaki ,  Tokuo Kure ,  Takahiro Okabe ,  Minoru Nagata

IPC分类号： H01L21/8222 ,  H01L21/033 ,  H01L21/3205 ,  H01L21/331 ,  H01L27/06 ,  H01L29/423 ,  H01L29/70 ,  H01L29/72 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735 ,  H01L23/48 ,  H01L29/04 ,  H01L29/34

CPC分类号： H01L29/66272 ,  H01L21/033 ,  H01L29/42304 ,  H01L29/72 ,  H01L29/732 ,  H01L29/735

摘要： A semiconductor device wherein the active regions of a transistor are formed in an opening provided in an insulating film, electrodes are led out by a polycrystalline silicon film formed on the insulating film, and the upper surfaces of the emitter and base electrodes and the exposed surface of the insulating film are substantially even.

摘要翻译： 一种半导体器件，其中晶体管的有源区形成在设置在绝缘膜中的开口中，电极由形成在绝缘膜上的多晶硅膜引出，发射极和基极的上表面和暴露表面 的绝缘膜基本上均匀。

公开(公告)号：US5061645A

公开(公告)日：1991-10-29

申请号：US498489

申请日：1990-03-26

申请人： Kazuo Nakazato ,  Tohru Nakamura ,  Masatoshi Matsuda ,  Takao Miyazaki ,  Tokuo Kure ,  Takahiro Okabe ,  Minoru Nagata

发明人： Kazuo Nakazato ,  Tohru Nakamura ,  Masatoshi Matsuda ,  Takao Miyazaki ,  Tokuo Kure ,  Takahiro Okabe ,  Minoru Nagata

IPC分类号： H01L21/8222 ,  H01L21/033 ,  H01L21/3205 ,  H01L21/331 ,  H01L27/06 ,  H01L29/423 ,  H01L29/70 ,  H01L29/72 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735

CPC分类号： H01L29/66272 ,  H01L21/033 ,  H01L29/42304 ,  H01L29/72 ,  H01L29/732 ,  H01L29/735

摘要： A method of manufacturing a bipolar transistor semiconductor device wherein the active regions of a transistor are formed in an opening provided in an insulating film, electrodes are led out by a polycrystalline silicon film formed on the insulating film, and the upper surfaces of the emitter and base electrodes and the exposed surface of the insulating film are substantially even.

公开(公告)号：US5109263A

公开(公告)日：1992-04-28

申请号：US556365

申请日：1990-07-24

申请人： Mitsuo Nanba ,  Tohru Nakamura ,  Kazuo Nakazato ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

发明人： Mitsuo Nanba ,  Tohru Nakamura ,  Kazuo Nakazato ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

IPC分类号： H01L21/331 ,  H01L21/762 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/76229 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/732

摘要： A vertical bipolar transistor arrangement in which the distance between the emitter and the isolation region is kept within a range determined by the sum of emitter depth and base width (i.e., the thickness of the base in the depth direction). This keeps the carriers given by the emitter from getting trapped inside, thereby preventing the cut-off frequency from dropping.

摘要翻译： 发射极和隔离区域之间的距离保持在由发射极深度和基底宽度（即，基底在深度方向上的厚度）确定的范围内的垂直双极晶体管布置。 这样可以防止发射器的载波被捕获到内部，从而防止截止频率的下降。

公开(公告)号：US4956688A

公开(公告)日：1990-09-11

申请号：US374570

申请日：1989-06-27

申请人： Noriyuki Honma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

发明人： Noriyuki Honma ,  Tohru Nakamura ,  Kazuo Nakazato ,  Motoaki Matsumoto ,  Tetsuya Hayashida ,  Masaharu Kubo ,  Kazuhiko Sagara

IPC分类号： H01L27/102 ,  H01L29/732

CPC分类号： H01L27/1025 ,  H01L29/7327

摘要： A bipolar memory of a construction having high immunity from soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuit of the memory cell, are inverted, and the load device thereof has a shielding arrangement for shielding the flip flop from the noise produced within the substrate. Either pnp type transistors or Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in the region where the device is provided. A reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.

摘要翻译： 提供了具有高抗免除由α射线引起的软误差的结构的双极记忆。 触发器的晶体管，即存储单元的基本电路被反转，并且其负载装置具有用于屏蔽触发器与基板内产生的噪声的屏蔽装置。 采用pnp型晶体管或肖特基势垒二极管作为负载器件。 在设置有器件的区域中形成掩埋层（通常为n型层）和反向导电型（通常为p型）的掺杂层。 跨越掩埋层和掺杂层施加反向偏压，以切断衬底内产生的噪声。

公开(公告)号：US4887145A

公开(公告)日：1989-12-12

申请号：US937610

申请日：1986-12-03

申请人： Katsuyoshi Washio ,  Tohru Nakamura ,  Kazuo Nakazato ,  Masatada Horiuchi ,  Tetsuya Hayashida

发明人： Katsuyoshi Washio ,  Tohru Nakamura ,  Kazuo Nakazato ,  Masatada Horiuchi ,  Tetsuya Hayashida

IPC分类号： H01L21/285 ,  H01L21/32 ,  H01L21/331 ,  H01L29/423 ,  H01L29/732 ,  H01L29/04

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/32 ,  H01L29/42304 ,  H01L29/7325

摘要： A bipolar transistor capable of operating at high speeds. In a bipolar transistor designed for operation at high speeds, a polycrystalline silicon layer used as a base electrode effects is a contact area with respect to the base region which lacks precision or tends to increase. Further, when the transistor is formed in a small size, the ratio of the contact area with respect to the polycrystalline area increases, making it difficult to increase the operation speed. In order to reduce the contact area of the polycrystalline silicon layer, this invention deals with the structure in which the polycrystalline silicon layer is brought into contact with a portion near the edge of the convex semiconductor layer maintaining a small size and a high precision.

摘要翻译： 能够高速运行的双极晶体管。 在设计用于高速运行的双极晶体管中，用作基极效应的多晶硅层是相对于缺少精度或倾向于增加的基极区域的接触面积。 此外，当晶体管形成为小尺寸时，接触面积相对于多晶面积的比率增加，使得难以提高操作速度。 为了减少多晶硅层的接触面积，本发明涉及多晶硅层与凸半导体层的边缘附近的部分接触的结构，保持小尺寸和高精度。

公开(公告)号：US4769687A

公开(公告)日：1988-09-06

申请号：US40125

申请日：1987-04-20

申请人： Kazuo Nakazato ,  Tohru Nakamura ,  Masataka Kato ,  Takahiro Okabe

发明人： Kazuo Nakazato ,  Tohru Nakamura ,  Masataka Kato ,  Takahiro Okabe

IPC分类号： H01L29/73 ,  H01L21/225 ,  H01L21/285 ,  H01L21/331 ,  H01L29/10 ,  H01L29/735 ,  H01L29/72 ,  H01L27/04 ,  H01L29/54

CPC分类号： H01L21/28525 ,  H01L21/2257 ,  H01L29/1008 ,  H01L29/735

摘要： A lateral bipolar transistor affording a good controllability for a base length is disclosed.In fabricating a lateral bipolar transistor by forming a single crystal column and disposing heavily doped polycrystalline regions on both sides of the column, contact surfaces between the single crystal column and the heavily doped polycrystalline regions are controlled by etching of an oxide film. The etching of the oxide film can provide a device of a precision higher than attained by controlling any other element.

摘要翻译： 公开了提供对基底长度的良好可控性的横向双极晶体管。 在通过形成单晶列并在柱的两侧设置重掺杂多晶区制造横向双极晶体管时，通过蚀刻氧化膜来控制单晶柱与重掺杂多晶区之间的接触表面。 氧化膜的蚀刻可以提供比通过控制任何其它元件获得的精度更高的装置。