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    Method of manufacturing non-volatile semiconductor memory device
    4.
    发明授权
    Method of manufacturing non-volatile semiconductor memory device 失效
    制造非易失性半导体存储器件的方法

    公开(公告)号：US5208173A

    公开(公告)日：1993-05-04

    申请号：US672631

    申请日：1991-03-20

    申请人： Seiji Yamada ,  Kiyomi Naruke

    发明人： Seiji Yamada ,  Kiyomi Naruke

    IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L21/28273

    摘要： The present invention provides a method of manufacturing a nonvolatile semiconductor memory device. In the method of the present invention. Arsenic ions are implanted into an element region of a silicon substrate so as to form a first impurity region. Then, an insulating film is formed on the silicon substrate in the element region, followed by forming a heat resistant film on the entire surface of the silicon substrate. Further, a resist film is formed on the silicon substrate, followed by patterning the resist film to form an opening on at least the first impurity region. After the patterning step, the heat resistant film positioned below the opening of the resist film is removed, followed by implanting phosphorus ions into the substrate using the patterned resist film as a mask so as to form a second impurity region. In the next step, the resist film is removed and, then, annealing is applied with the heat resistant film used as a mask. After the annealing step, the resist film is removed, and an annealing is performed with the heat resistant film used as a mask, followed by removing the insulating film using the heat resistant film as a mask. Finally, a tunnel oxide film is formed on that portion of the silicon substrate, followed by forming an electrode on the tunnel oxide film so as to manufacture a desired nonvolatile semiconductor memory device.

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
    6.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20110024824A1

    公开(公告)日：2011-02-03

    申请号：US12820351

    申请日：2010-06-22

    申请人： Yasuhiro SHIMURA ,  Takashi Izumida ,  Mutsuo Morikado ,  Kiyomi Naruke

    发明人： Yasuhiro SHIMURA ,  Takashi Izumida ,  Mutsuo Morikado ,  Kiyomi Naruke

    IPC分类号： H01L29/792 ,  H01L21/28

    CPC分类号： H01L29/42324 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7881

    摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer and a transistor. The transistor includes: a source region, a drain region, and a channel region provided in the semiconductor layer, the channel region being between the source and drain regions; a gate insulating film provided on the channel region; a charge layer provided on the gate insulating film, the charge layer having a side portion and a apical portion;an inter-electrode insulating film covering the side portion and the apical portion; and a control gate provided on the inter-electrode insulating film. The control gate includes: a side-portion conductive layer opposing the side portion; and an apical-portion conductive layer opposing the apical portion.The apical-portion conductive layer has a work function higher than a work function of the charge layer and higher than a work function of the side-portion conductive layer.

    摘要翻译： 根据一个实施例，非易失性半导体存储器件包括半导体层和晶体管。 晶体管包括：源极区，漏极区和设置在半导体层中的沟道区，沟道区位于源区和漏区之间; 设置在沟道区上的栅极绝缘膜; 设置在所述栅极绝缘膜上的电荷层，所述电荷层具有侧部和顶部; 覆盖所述侧部和所述顶部的电极间绝缘膜; 以及设置在电极间绝缘膜上的控制栅极。 控制门包括：与侧部相对的侧部导电层; 以及与顶端部分相对的顶端部导电层。 顶部导电层的功函数高于电荷层的功函数，高于侧面导电层的功函数。

    Nonvolatile semiconductor memory device which erases data in units of one block including a number of memory cells, and data erasing method of the nonvolatile semiconductor memory device
    7.
    发明授权
    Nonvolatile semiconductor memory device which erases data in units of one block including a number of memory cells, and data erasing method of the nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件，其以包含多个存储单元的一个块为单位擦除数据，以及非易失性半导体存储器件的数据擦除方法

    公开(公告)号：US07215576B2

    公开(公告)日：2007-05-08

    申请号：US11213889

    申请日：2005-08-30

    申请人： Hiroshi Watanabe ,  Hideo Kato ,  Takamichi Kasai ,  Kiyomi Naruke ,  Hiroyuki Sasaki

    发明人： Hiroshi Watanabe ,  Hideo Kato ,  Takamichi Kasai ,  Kiyomi Naruke ,  Hiroyuki Sasaki

    IPC分类号： G11C11/34 ,  G11C16/06 ,  G11C16/04

    CPC分类号： G11C16/3404

    摘要： In a data erasing method of a nonvolatile semiconductor memory device, cells are subjected to the processings of executing programming by applying a voltage to the cells to set their threshold values at a given level or more, erasing the cells to set their threshold values at a lower level or less, executing weak programming once on a cell whose threshold value is lower than a further lower level, by applying a lower voltage to the cell, repeating the weak programming on the cell when its threshold value is still lower than the further lower level, until the value reaches the further lower level or more, verifying whether a cell is present whose threshold value is higher than the lower level, and returning the processing to the processing of setting the threshold values of the cells at the lower level or less, when verifying that the above cell is present.

    摘要翻译： 在非易失性半导体存储器件的数据擦除方法中，通过向单元施加电压来对单元进行执行编程的处理，以将它们的阈值设置在给定等级或更多的值，擦除单元以将其阈值设置在 较低级别或更低级别，通过对小区施加较低的电压，在阈值低于更低级别的小区上执行弱编程一次，当其阈值仍然低于另一较低级别时，对小区重复弱编程 级，直到该值达到更低级别或更高级别，验证阈值是否高于较低级别的单元存在，并且将该处理返回到将小区的阈值设置为较低级别或更低级别的处理 ，当验证上述单元格是否存在时。

    Method of making implanted device regions in a semiconductor using a master mask member
    8.
    发明授权
    Method of making implanted device regions in a semiconductor using a master mask member 失效
    使用主掩模构件在半导体中制造植入的器件区域的方法

    公开(公告)号：US4675981A

    公开(公告)日：1987-06-30

    申请号：US802163

    申请日：1985-11-25

    申请人： Kiyomi Naruke

    发明人： Kiyomi Naruke

    IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/336 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

    CPC分类号： H01L29/66575 ,  H01L21/266 ,  H01L21/76216 ,  H01L29/78609 ,  H01L29/78654 ,  H01L29/78657 ,  Y10S148/082 ,  Y10S148/104

    摘要： A method of manufacturing an MOS transistor comprises the steps of forming a silicon nitride film on a central portion of a P-type silicon substrate, forming a first resist pattern on the semiconductor substrate and the film using a mask member having a central opening, ion-implanting a first impurity of P-type into the substrate using the first resist pattern and the film as masks, removing the first resist pattern from the semiconductor substrate, forming a second resist pattern on the substrate using the mask member, and ion-implanting a second impurity of P-type into the substrate at a low acceleration voltage using the second resist pattern as a mask. Then, a gate electrode is formed on the substrate and an impurity of n-type is implanted into the substrate to form source and drain regions of n-type.

    摘要翻译： 一种制造MOS晶体管的方法包括以下步骤：在P型硅衬底的中心部分上形成氮化硅膜，在半导体衬底上形成第一抗蚀剂图案，并使用具有中心开口的掩模构件 使用第一抗蚀剂图案和膜作为掩模将P型的第一杂质植入基板中，从半导体基板去除第一抗蚀剂图案，使用掩模构件在基板上形成第二抗蚀剂图案，以及离子注入 使用第二抗蚀剂图案作为掩模，以低加速电压将P型第二杂质掺入到衬底中。 然后，在基板上形成栅电极，将n型杂质注入基板，形成n型的源区和漏区。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20130077404A1

    公开(公告)日：2013-03-28

    申请号：US13424741

    申请日：2012-03-20

    申请人： Hidefumi Nawata ,  Kiyomi Naruke

    发明人： Hidefumi Nawata ,  Kiyomi Naruke

    IPC分类号： G11C16/10

    CPC分类号： G11C16/10 ,  G11C16/3418 ,  G11C16/3454

    摘要： A nonvolatile semiconductor memory device according to one embodiment includes: memory cells; word lines connected to the memory cells; and a control circuit configured to control a data read operation. When controlling the data read operation, the control circuit applies one of read voltages to a selected word line, applies a first read pass voltage to a first non-selected word line connected to one of data-written memory cells, and applies a second read pass voltage to a second non-selected word line connected to a non-written memory cell. Each of the read voltages is set to a voltage between two threshold voltage distributions. The first read pass voltage is set so that the data-written memory cells become conductive. The second read pass voltage is set so as to be lower than a highest read voltage, the highest read voltage being the highest voltage among the read voltages.

    摘要翻译： 根据一个实施例的非易失性半导体存储器件包括：存储单元; 连接到存储单元的字线; 以及控制电路，被配置为控制数据读取操作。 当控制数据读取操作时，控制电路将一个读取电压施加到所选择的字线，将第一读取通过电压施加到连接到数据写入存储器单元之一的第一未选择字线，并施加第二读取 将电压传递到连接到非写入存储单元的第二未选择字线。 每个读取电压被设置为两个阈值电压分布之间的电压。 第一读通过电压被设置为使得数据写入的存储器单元变为导通。 第二读取通过电压被设置为低于最高读取电压，最高读取电压是读取电压中的最高电压。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    10.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
    非易失性半导体存储器件

    公开(公告)号：US20110001180A1

    公开(公告)日：2011-01-06

    申请号：US12768086

    申请日：2010-04-27

    申请人： Kazunori MASUDA ,  Mutsuo Morikado ,  Kiyomi Naruke

    发明人： Kazunori MASUDA ,  Mutsuo Morikado ,  Kiyomi Naruke

    IPC分类号： H01L27/115 ,  H01L21/8247

    CPC分类号： H01L27/11521 ,  H01L27/11524

    摘要： In a nonvolatile semiconductor memory device having a plurality of nonvolatile memory cells integrated on a semiconductor substrate, each of the memory cells includes a tunnel insulating film formed on the semiconductor substrate, a floating gate electrode formed on the tunnel insulating film, a first interelectrode insulating film formed on the upper surface of the floating gate electrode, a second interelectrode insulating film formed to cover the side surfaces of the floating gate electrode and the first interelectrode insulating film, and a control gate electrode formed on the second interelectrode insulating film.

    摘要翻译： 在具有集成在半导体基板上的多个非易失性存储单元的非易失性半导体存储器件中，每个存储单元包括形成在半导体衬底上的隧道绝缘膜，形成在隧道绝缘膜上的浮置栅电极，第一电极间绝缘膜 形成在浮栅电极的上表面上的膜，形成为覆盖浮栅和第一电极间绝缘膜的侧表面的第二电极间绝缘膜，以及形成在第二电极间绝缘膜上的控制栅电极。