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公开(公告)号：US20130093101A1
公开(公告)日：2013-04-18
申请号：US13427293
申请日：2012-03-22
IPC分类号： H01L23/48
CPC分类号： H01L24/49 , H01L23/3121 , H01L24/06 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/04042 , H01L2224/06155 , H01L2224/06165 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/49109 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/06568 , H01L2924/00014 , H01L2924/1431 , H01L2924/1434 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： According to one embodiment, a semiconductor device is provided. The semiconductor device includes a package substrate; a first semiconductor chip mounted on the package substrate and adapted to include a plurality of first bonding pads arranged in a first order on an upper surface; a second semiconductor chip arranged on the first semiconductor chip and adapted to include a plurality of second bonding pads arranged in the first order on an upper surface; and first bonding wires configured to connect each of the plurality of first bonding pads and the plurality of second bonding pads.
摘要翻译： 根据一个实施例，提供一种半导体器件。 半导体器件包括封装衬底; 第一半导体芯片，其安装在所述封装基板上，并且适于包括在上表面上以一级布置的多个第一接合焊盘; 第二半导体芯片，布置在第一半导体芯片上并且适于包括在上表面上以一级布置的多个第二接合焊盘; 以及第一接合线，其被配置为连接所述多个第一接合焊盘和所述多个第二接合焊盘中的每一个。
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公开(公告)号：US5349553A
公开(公告)日：1994-09-20
申请号：US77719
申请日：1993-06-17
申请人： Seiji Yamada , Masamitsu Oshikiri
发明人： Seiji Yamada , Masamitsu Oshikiri
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/40 , G11C11/24
CPC分类号： G11C16/0416
摘要： A nonvolatile semiconductor memory device comprises a memory cell array including memory cell transistors having a lamination gate structure are arranged in a matrix manner at the position where a word line and a bit line cross each other. A lower voltage than a threshold voltage is applied to the word line selected at the time of a reading mode in a state that no electrical charge is stored in the floating gate.
摘要翻译： 非易失性半导体存储器件包括具有叠层栅极结构的存储单元晶体管的存储单元阵列以矩阵方式布置在字线和位线彼此交叉的位置。 在读取模式时，在浮动栅极中不存储电荷的状态下，将比阈值电压更低的电压施加到所选择的字线。
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公开(公告)号：US5751636A
公开(公告)日：1998-05-12
申请号：US785397
申请日：1997-01-21
申请人： Kiyomi Naruke , Tomoko Suzuki , Seiji Yamada , Etsushi Obi , Masamitsu Oshikiri
发明人： Kiyomi Naruke , Tomoko Suzuki , Seiji Yamada , Etsushi Obi , Masamitsu Oshikiri
IPC分类号： G11C16/16 , G11C16/34 , H01L27/115 , H01L29/788 , G11C7/00
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404 , H01L27/115 , H01L29/7885
摘要： In this invention, charges are extracted from the charge storage portion by means of F-N tunnel current, and then avalanche hot carriers are injected into the storage portion.
摘要翻译： 在本发明中，通过F-N隧道电流从电荷存储部分提取电荷，然后将雪崩热载流子注入存储部分。
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公开(公告)号：US5623445A
公开(公告)日：1997-04-22
申请号：US440253
申请日：1995-05-12
申请人： Kiyomi Naruke , Tomoko Suzuki , Seiji Yamada , Etsushi Obi , Masamitsu Oshikiri
发明人： Kiyomi Naruke , Tomoko Suzuki , Seiji Yamada , Etsushi Obi , Masamitsu Oshikiri
IPC分类号： G11C16/16 , G11C16/34 , H01L27/115 , H01L29/788 , G11C11/40
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404 , H01L27/115 , H01L29/7885
摘要： In this invention, charges are extracted from the charge storage portion by means of F-N tunnel current, and then avalanche hot carriers are injected into the storage portion.
摘要翻译： 在本发明中，通过F-N隧道电流从电荷存储部分提取电荷，然后将雪崩热载流子注入存储部分。
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公开(公告)号：US5452248A
公开(公告)日：1995-09-19
申请号：US903949
申请日：1992-06-26
申请人： Kiyomi Naruke , Tomoko Suzuki , Seiji Yamada , Etsushi Obi , Masamitsu Oshikiri
发明人： Kiyomi Naruke , Tomoko Suzuki , Seiji Yamada , Etsushi Obi , Masamitsu Oshikiri
IPC分类号： G11C16/16 , G11C16/34 , H01L27/115 , H01L29/788 , G11C16/02
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404 , H01L27/115 , H01L29/7885
摘要： In this invention, charges are extracted from the charge storage portion by means of F-N tunnel current, and then avalanche hot carriers are injected into the storage portion.
摘要翻译： 在本发明中，通过F-N隧道电流从电荷存储部分提取电荷，然后将雪崩热载流子注入存储部分。
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