-
公开(公告)号：US5166867A
公开(公告)日：1992-11-24
申请号：US27062
申请日：1987-03-17
CPC分类号： H01R12/7088 , H05K1/0263 , H05K1/0271 , H05K2201/10272 , H05K3/341
摘要： A massive bus bar for supplying a determined power voltage to a circuit component mounted on a rigid circuit board having a conductor layer connecting the component to a bus bar connecting pad formed on the surface of the board. Plurality of first notches extend through a main surface of the bus bar from a common longitudinal edge, perpendicularly to the longitudinal axis of the bus bar and throughout the full longitudinal extent of the bus bar, and define a plurality of posts which are secured at their bottom surfaces to the conductive pads on the circuit board surface. The first notches facilitate flexing of the bus bar and reduce stresses otherwise produced due to the rigid connection of the bus bar to the circuit board, while not significantly diminishing the current handling capability of the bus bar. Second and third pluralities of orthogonally extending notches, respectively parallel and perpendicular to the longitudinal axis of the bus bar, are formed in the bottom surfaces of each post, further reducing stresses.
摘要翻译： 一种用于向安装在刚性电路板上的电路部件提供确定的电源电压的巨大汇流条，该电路部件具有将该部件连接到形成在该电路板表面上的汇流条连接焊盘的导体层。 多个第一凹槽从母线的主表面延伸通过垂直于汇流条的纵向轴线的公共纵向边缘并且在整个母线的整个纵向范围内延伸，并且限定多个柱， 底表面到电路板表面上的导电焊盘。 第一个凹口有助于母线的弯曲，并减少由于母线与电路板的刚性连接而产生的应力，同时不会显着降低母线的当前处理能力。 分别平行且垂直于汇流条的纵向轴线的第二和第三多个正交延伸的凹口形成在每个柱的底表面中，进一步减小了应力。
-
2.发明授权
公开(公告)号：US4707622A
公开(公告)日：1987-11-17
申请号：US815061
申请日：1985-12-31
申请人： Hisoka Takao , Toshiro Sato , Seiichi Saito , Toshinari Hayashi
发明人： Hisoka Takao , Toshiro Sato , Seiichi Saito , Toshinari Hayashi
IPC分类号： H03K19/0944 , H03K19/0952 , H03K19/094
CPC分类号： H03K19/09443 , H03K19/0952
摘要： A logic circuit includes an inverter circuit including a first enhancement type field effect transistor having a gate connected to an input, and a first depletion type transistor having a gate and a source which are directly connected to a drain of the first enhancement type field effect transistor. A source follower circuit including a second enhancement type field effect transistor having a gate is connected to a connecting point of the first enhancement type field effect transistor and the first depletion type field effect transistor. A second depletion type field effect transistor having a gate and a source which are directly connected to each other has a drain which is connected to a source of the second enhancement type field effect transistor. A first power source is connected to the drains of the first depletion type field effect transistor and the second enhancement type field effect transistor and a second power source is connected to the sources of the first enhancement type field effect transistor and the second depletion type field effect transistor. An output is formed at the connecting point of the second enhancement type field effect transistor and the second depletion type field effect type transistor.
摘要翻译： 逻辑电路包括反相器电路，其包括具有连接到输入端的栅极的第一增强型场效应晶体管和具有栅极和源极的第一耗尽型晶体管，其直接连接到第一增强型场效应晶体管的漏极 。 包括具有栅极的第二增强型场效应晶体管的源极跟随器电路连接到第一增强型场效应晶体管和第一耗尽型场效应晶体管的连接点。 具有彼此直接连接的栅极和源极的第二耗尽型场效应晶体管具有连接到第二增强型场效应晶体管的源极的漏极。 第一电源连接到第一耗尽型场效应晶体管和第二增强型场效应晶体管的漏极，第二电源连接到第一增强型场效应晶体管的源极和第二衰减型场效应 晶体管。 在第二增强型场效应晶体管和第二耗尽型场效应晶体管的连接点处形成输出。
-
公开(公告)号：US20140199040A1
公开(公告)日：2014-07-17
申请号：US14116384
申请日：2012-05-10
IPC分类号： G02B6/02
CPC分类号： G02B6/02395 , C03C25/106 , C03C25/40 , G02B6/4436
摘要： Provided is an optical fiber which is provided with heat resistance and productivity and in which a transmission loss is suppressed even in a high-temperature environment. It has, on an outer periphery of a glass fiber composed of a core part and a cladding part, a coating layer made by crosslinking an energy-curable resin composition containing a silicon compound, in which the silicon compound contained in the energy-curable resin composition of the coating layer as an outermost layer has a specified structure having a cyclic silicone site having an epoxy group and a linear silicone site, with the content of the cyclic silicone site in the compound being from 10 to 30% by mass.
摘要翻译： 提供具有耐热性和生产率的光纤，即使在高温环境下也能抑制传输损失。 在由芯部和包层部分构成的玻璃纤维的外周上，通过将含有硅化合物的能量固化树脂组合物交联而制成的涂层，其中包含在能量固化树脂中的硅化合物 作为最外层的涂层的组成具有具有环氧基和环状硅氧烷部位的环状硅氧烷部位的特定结构，化合物中的环状硅氧烷部位的含量为10〜30质量％。
-
4.发明授权Apparatus and method for controlling grille aperture ratios of a plurality of air transfer grilles 有权用于控制多个空气传送格栅的格栅孔径比的装置和方法公开(公告)号：US08768519B2
公开(公告)日：2014-07-01
申请号：US12782878
申请日：2010-05-19
申请人： Ikuro Nagamatsu , Junichi Ishimine , Seiichi Saito , Masahiro Suzuki , Tadashi Katsui , Yuji Ohba , Nobuyoshi Yamaoka , Akira Ueda , Yasushi Uraki
发明人： Ikuro Nagamatsu , Junichi Ishimine , Seiichi Saito , Masahiro Suzuki , Tadashi Katsui , Yuji Ohba , Nobuyoshi Yamaoka , Akira Ueda , Yasushi Uraki
CPC分类号： H05K7/20836
摘要： An apparatus for controlling grille aperture ratios of a plurality of air transfer grilles which are installed in a room, includes a determining unit for determining target grille air volumes of air blowing to the racks, for determining simulation air volumes of air blowing from the air transfer grilles on the basis of the target grille air volumes so that each of air of the target grille air volumes are blown to the racks, and for determining grille aperture ratios for each of the air transfer grilles on the basis of the plurality of simulation air volumes so that each of the amounts of air blowing from the air transfer grilles is replaced by each of the simulation air volumes, and a controller for controlling each of the grille aperture ratios of the air transfer grilles on the basis of each of the determined grille aperture ratios.
摘要翻译： 一种用于控制安装在房间中的多个空气传送格栅的格栅孔径比的装置，包括：确定单元，用于确定向机架吹送的空气的目标格栅空气体积，用于确定从空气传送中吹出的空气的模拟空气体积 基于目标格栅空气体积格栅，使得目标格栅空气体积的每个空气被吹送到机架，并且基于多个模拟空气体积确定每个空气传送格栅的格栅孔径比 使得从空气传送格栅吹出的每个空气量被每个模拟空气量所取代;以及控制器，用于基于每个确定的格栅孔径来控制空气传送格栅的每个格栅孔径比 比率。
-
公开(公告)号：US08063768B2
公开(公告)日：2011-11-22
申请号：US11792057
申请日：2005-04-14
IPC分类号： H04Q1/30
CPC分类号： H04B3/56 , H04B2203/5483
摘要： Provided is a modem apparatus of power line communication using a power line as a transmission path. The modem apparatus includes: an amplifier for amplifying communication signals and outputting a differential signal obtained from a pair of output signals having a phase difference of 180 degrees therebetween; a signal transformer for applying the amplified communication signals to the power lines; and a balance circuit connected at the primary side of the signal transformer, for enhancing circuit balancing. The balance circuit is constituted by a variable element capable of changing an element value, and there is provided a common mode detecting circuit that detects a common mode current flowing through the secondary side of the signal transformer and that changes the element value of the variable element of the balance circuit such that the detected common mode current becomes small.
摘要翻译： 提供了使用电力线作为传输路径的电力线通信的调制解调器装置。 调制解调器装置包括：放大器，用于放大通信信号并输出从具有180度相位差的一对输出信号获得的差分信号; 用于将放大的通信信号施加到电力线的信号变换器; 以及连接在信号变压器初级侧的平衡电路，用于增强电路平衡。 平衡电路由能够改变元件值的可变元件构成，并且提供了共模检测电路，其检测流过信号变压器次级侧的共模电流，并且改变可变元件的元件值 使得检测到的共模电流变小。
-
公开(公告)号：US08018784B2
公开(公告)日：2011-09-13
申请号：US12636528
申请日：2009-12-11
CPC分类号： G06F1/3253 , G06F1/3237 , Y02D10/128 , Y02D10/151
摘要： To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.Ina data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
摘要翻译： 提高从高速电路块访问低速电路块的速度，而不会显着增加功耗。 Ina数据处理器具有总线控制器，其执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路，时序控制电路设置在 外围电路和总线控制器以及总线控制器响应于来自外围电路的读取指令，使定时控制电路与外围电路的高周期同步地将外围电路保持的数据输出到总线控制器， 响应于针对外围电路的写入指令，使定时控制电路开始与高速时钟信号的周期同步地写入外围电路，并且与该时钟信号同步地终止写入 周期的低速时钟信号。
-
公开(公告)号：US20100318329A1
公开(公告)日：2010-12-16
申请号：US12787587
申请日：2010-05-26
申请人： Yasushi Uraki , Junichi Ishimine , Ikuro Nagamatsu , Masahiro Suzuki , Tadashi Katsui , Yuji Ohba , Nobuyoshi Yamaoka , Akira Ueda , Sayoko Tominaga , Seiichi Saito
发明人： Yasushi Uraki , Junichi Ishimine , Ikuro Nagamatsu , Masahiro Suzuki , Tadashi Katsui , Yuji Ohba , Nobuyoshi Yamaoka , Akira Ueda , Sayoko Tominaga , Seiichi Saito
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F2217/16 , G06Q10/06
摘要： There are included a location-information management unit that manages location information of devices arranged in a spatial layout on a screen, a device-feature management unit that manages device features of the devices, a guide-information generation unit that reads the location information and the device features of the devices arranged in the spatial layout from the location-information management unit and the device-feature management unit respectively and generates device-layout guide information allowing for the device features of the devices based on the read location information and device features of the devices, and a monitor unit that guides and displays the device-layout guide information generated by the guide-information generation unit.
摘要翻译： 包括管理屏幕上以空间布局布置的设备的位置信息的位置信息管理单元，管理设备的设备特征的设备特征管理单元，读取位置信息的引导信息生成单元和 分别从位置信息管理单元和设备特征管理单元以空间布局布置的设备的设备特征，并且基于读取的位置信息和设备特征生成允许设备的设备特征的设备布局指南信息 以及引导和显示由引导信息生成单元生成的设备布局指南信息的监视器单元。
-
公开(公告)号：US07595357B2
公开(公告)日：2009-09-29
申请号：US10560815
申请日：2004-07-15
申请人： Seiichi Saito
发明人： Seiichi Saito
CPC分类号： C08L61/04 , C08K5/5399 , H05K1/0326 , C08L61/14
摘要： A vinyl ether curing composition is formed from a polyvalent vinyl ether compound, a polyvalent phenolic compound and a flame retardant. The composition may contain 10 to 30 parts by weight of a phosphorus-based flame retardant as the flame retardant per 100 parts by weight of the total of the polyfunctinoal vinyl ether compound and the polyhydric phenol compound. This vinyl ether curing composition allows the formation of a cured product with a low dielectric constant.
摘要翻译： 乙烯基醚固化组合物由多价乙烯基醚化合物，多价酚类化合物和阻燃剂形成。 该组合物可以含有10〜30重量份作为阻燃剂的磷系阻燃剂，相对于100重量份的聚多角质乙烯基醚化合物和多元酚化合物的总量。 该乙烯基醚固化组合物允许形成具有低介电常数的固化产物。
-
公开(公告)号：US20090066401A1
公开(公告)日：2009-03-12
申请号：US12298673
申请日：2007-04-10
申请人： Seiichi Saito
发明人： Seiichi Saito
IPC分类号： H03K17/16
CPC分类号： H03K17/693 , H03F3/38 , H03K17/691
摘要： An analog insulation multiplexer not causing magnetic saturation even if a small transformer is used and having a wide use temperature range. The analog insulation multiplexer includes: a first switching element for generating a drive control signal in accordance with an external signal; a drive insulation transformer for receiving the drive control signal on a primary side via a first resistor and for delivering an insulated drive control signal from a secondary side; a second switching element for chopping an analog signal input in accordance with the insulated drive control signal; and an analog signal insulation transformer for delivering an insulated chopped analog signal on a secondary side. The analog insulation multiplexer further includes a secondary side output adjusting circuit having a second resistor connected, on the primary side of the drive insulation transformer, in parallel to the first resistor and a capacitor having one end connected to a ground and another end connected in series to the second resistor.
摘要翻译： 即使使用小型变压器并具有广泛的使用温度范围，模拟绝缘多路复用器也不会引起磁饱和。 模拟绝缘多路复用器包括：第一开关元件，用于根据外部信号产生驱动控制信号; 驱动绝缘变压器，用于经由第一电阻器在初级侧接收驱动控制信号，并用于从次级侧传送绝缘的驱动控制信号; 第二开关元件，用于根据绝缘驱动控制信号斩波模拟信号输入; 以及用于在次级侧传送绝缘的斩波模拟信号的模拟信号绝缘变压器。 模拟绝缘多路复用器还包括二次侧输出调节电路，其具有在驱动绝缘变压器的初级侧与第一电阻器并联的第二电阻器，以及电容器，其一端连接到地，另一端串联连接 到第二个电阻。
-
公开(公告)号：US07501910B2
公开(公告)日：2009-03-10
申请号：US11359510
申请日：2006-02-23
申请人： Keitaro Yamagishi , Seiichi Saito
发明人： Keitaro Yamagishi , Seiichi Saito
IPC分类号： H01P1/26
CPC分类号： H04L25/0298 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2924/19105 , H04L25/0292 , H05K1/0237 , H05K1/0246 , H05K1/0298 , H05K2201/10022 , H05K2201/10734 , H01L2224/0401
摘要： Provided is a signal transmission circuit capable of realizing the same effects as those in a conventional manner that employs a complicated circuit by using no complicated circuit, that is, by a simple circuit. The signal transmission circuit includes: a transmission path having a first impedance; a terminating resistor having a predetermined resistance; a transmission path having a second impedance, which is connected to the transmission path and the terminating resistor, the second impedance being higher than both of the first impedance and the predetermined resistance; and an input buffer for receiving a signal at a connection portion of the transmission path and the transmission path.
摘要翻译： 提供一种信号传输电路，其能够实现与通过不使用复杂电路即简单电路采用复杂电路的常规方式相同的效果。 信号传输电路包括：具有第一阻抗的传输路径; 具有预定电阻的终端电阻器; 具有第二阻抗的传输路径，其连接到传输路径和终端电阻器，第二阻抗高于第一阻抗和预定电阻两者; 以及用于在传输路径和传输路径的连接部分处接收信号的输入缓冲器。
-
-
-
-
-
-
-
-
-
搜索结果
104 条记录 (耗时 0.032 秒)
