公开(公告)号：US20120280231A1

公开(公告)日：2012-11-08

申请号：US13521961

申请日：2010-03-15

申请人： Kiyoto Ito ,  Takanobu Tsunoda ,  Makoto Saen

发明人： Kiyoto Ito ,  Takanobu Tsunoda ,  Makoto Saen

IPC分类号： H01L23/52 ,  H01L21/66

CPC分类号： G01R31/318536 ,  G01R31/318513 ,  H01L25/0657 ,  H01L27/0207 ,  H01L27/092 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06596

摘要： It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop (31b) by use of which either of a scan chain within a semiconductor chip (LSI_B), and a scan chain across plural semiconductor chips (LSI_A and LSI_B) can be made up.

摘要翻译： 对于跨越多个芯片的组合逻辑电路进行测试和分析是困难的，因此，提供了一种触发器（31b），其使用半导体芯片内的扫描链 LSI_B），并且可以构成跨越多个半导体芯片（LSI_A和LSI_B）的扫描链。

公开(公告)号：US08698140B2

公开(公告)日：2014-04-15

申请号：US13521961

申请日：2010-03-15

申请人： Kiyoto Ito ,  Takanobu Tsunoda ,  Makoto Saen

发明人： Kiyoto Ito ,  Takanobu Tsunoda ,  Makoto Saen

IPC分类号： H01L23/58

CPC分类号： G01R31/318536 ,  G01R31/318513 ,  H01L25/0657 ,  H01L27/0207 ,  H01L27/092 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06596

摘要： It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop (31b) by use of which either of a scan chain within a semiconductor chip (LSI_B), and a scan chain across plural semiconductor chips (LSI_A and LSI_B) can be made up.

摘要翻译： 对于跨越多个芯片的组合逻辑电路进行测试和分析是困难的，因此，提供了一种触发器（31b），其使用半导体芯片内的扫描链 LSI_B），并且可以构成跨越多个半导体芯片（LSI_A和LSI_B）的扫描链。

公开(公告)号：US20110042825A1

公开(公告)日：2011-02-24

申请号：US12916503

申请日：2010-10-30

申请人： KIYOTO ITO ,  Makoto Saen ,  Yuki Kuroda

发明人： KIYOTO ITO ,  Makoto Saen ,  Yuki Kuroda

IPC分类号： H01L25/065

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/063 ,  H01L23/544 ,  H01L23/552 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2224/0554 ,  H01L2224/05571 ,  H01L2224/16145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction. Communication between the processor LSI 100 and the memory LSI 200 in the same combination is performed by a dedicated electrode provided therebetween, and communication between processor LSIs 100 and communication from the processor LSI 100 to the outside are performed by a through silicon via for signal 11 which passes through all the LSIs.

摘要翻译： 在堆叠多个存储器LSI和多个处理器LSI的半导体器件中，随着堆叠层数的增加，存储器LSI和处理器LSI之间的数据的通信距离将增加。 因此，用于通信的布线的寄生电容和寄生电阻增加，结果整个系统的功率和速度性能将降低。 堆叠处理器LSI 100和存储器LSI 200的组合中的至少两个或更多个，并且相同组合的处理器LSI 100和存储器LSI 200在垂直方向上彼此相邻堆叠。 通过设置在其间的专用电极来执行处理器LSI 100和存储器LSI 200之间的相同组合的通信，并且处理器LSI 100之间的通信以及从处理器LSI 100到外部的通信由用于信号11的贯穿硅通道 通过所有的LSI。

公开(公告)号：US09144908B2

公开(公告)日：2015-09-29

申请号：US14114208

申请日：2012-04-18

申请人： Makoto Saen ,  Kiyoto Ito ,  Yoshimitsu Yanagawa ,  Tomomi Takahashi

发明人： Makoto Saen ,  Kiyoto Ito ,  Yoshimitsu Yanagawa ,  Tomomi Takahashi

IPC分类号： B25J15/00 ,  B25J19/00 ,  B25J15/08 ,  B25J15/02 ,  B25J13/08 ,  G01L5/22 ,  B25J9/16 ,  G01L5/00

CPC分类号： B25J15/0253 ,  B25J9/1612 ,  B25J13/083 ,  B25J13/085 ,  G01L5/009 ,  G01L5/228 ,  Y10S901/32 ,  Y10S901/34 ,  Y10S901/47

摘要： A manipulator device has an arm portion and a hand portion The hand portion includes one or more finger portions that manipulate a target object. Each finger portion includes a slip sensor and multiple contact sensors, with at least one contact sensor at a position proximate to the slip sensor and at least another contact sensor at a position remote from the slip sensor. When the contact sensors at the positions remote from the slip sensor detect contact of the target object and the contact sensors arranged at the positions proximate to the slip sensors do not detect contact, a position of the finger portion is moved by a distance corresponding to the distance between the contact sensors detecting contact of the target object and the contact sensors arranged at the positions proximate to the slip such that a detecting position of the slip sensor is coincident with a position of the target object.

摘要翻译： 操纵器装置具有臂部和手部。手部包括操纵目标物体的一个或多个手指部。 每个手指部分包括滑动传感器和多个接触传感器，其中至少一个接触传感器位于靠近滑动传感器的位置处，并且至少另一个接触传感器位于远离滑移传感器的位置。 当远离滑动传感器的位置处的接触传感器检测到目标物体的接触点和布置在靠近滑动传感器的位置处的接触传感器没有检测到接触时，手指部分的位置移动相应于 接触传感器之间的距离检测目标物体的接触点和布置在接近滑动位置的接触传感器之间的距离，使得滑动传感器的检测位置与目标物体的位置一致。

公开(公告)号：US20110309359A1

公开(公告)日：2011-12-22

申请号：US13148993

申请日：2009-02-27

申请人： Makoto Saen ,  Kenichi Osada ,  Kiyoto Ito

发明人： Makoto Saen ,  Kenichi Osada ,  Kiyoto Ito

IPC分类号： H01L23/58

CPC分类号： G01R31/318513 ,  G11C5/04 ,  G11C29/02 ,  G11C29/025 ,  H01L2224/16145 ,  H01L2224/16225

摘要： In a test method of stacked LSIs connected by Through Silicon Vias, it is difficult to perform a failure diagnosis by using a conventional device test method to only one side of a silicon wafer, there is a possibility of yield degradation at a stacking time of LSIs, and a plurality of LSIs is connected to one Through Silicon Via so that it is necessary to select and remedy a defective Through Silicon Via taking into account all the device states. These problems cannot be solved by conventional test methods. Therefore, for a device test of a Through Silicon Via through a plurality of chips, a circuit that generates a time-series test pattern having both 0 and 1 values for a delay fault test is added to a circuit portion that transmits data to a Through Silicon Via in the stacked LSIs, and a circuit that receives the test pattern and compares the pattern received with a fixed pattern for a match to detect a defect of a Through Silicon Via is added to a circuit portion that receives data from a Through Silicon Via in the stacked LSIs.

摘要翻译： 在通过硅通孔连接的层叠LSI的测试方法中，仅通过使用传统的器件测试方法仅对硅晶片的一侧进行故障诊断是困难的，因此在LSI的堆叠时间内产生劣化的可能性 ，并且多个LSI连接到一个通硅通孔，使得有必要考虑到所有器件状态来选择和补救有缺陷的Through Silicon Via。 这些问题不能用传统的测试方法来解决。 因此，对于通过多个芯片的通孔硅器件的器件测试，产生用于延迟故障测试的具有0和1值的时间序列测试图案的电路被添加到电路部分，该电路部分将数据发送到通 在层叠的LSI中的硅通孔，以及接收测试图案并将接收的模式与用于匹配的固定模式进行比较以检测通硅通孔的缺陷的电路被添加到从直通硅通道接收数据的电路部分 在堆叠的LSI中。

公开(公告)号：US07834440B2

公开(公告)日：2010-11-16

申请号：US12466018

申请日：2009-05-14

申请人： Kiyoto Ito ,  Makoto Saen ,  Yuki Kuroda

发明人： Kiyoto Ito ,  Makoto Saen ,  Yuki Kuroda

IPC分类号： H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/063 ,  H01L23/544 ,  H01L23/552 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2224/0554 ,  H01L2224/05571 ,  H01L2224/16145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction. Communication between the processor LSI 100 and the memory LSI 200 in the same combination is performed by a dedicated electrode provided therebetween, and communication between processor LSIs 100 and communication from the processor LSI 100 to the outside are performed by a through silicon via for signal 11 which passes through all the LSIs.

摘要翻译： 在堆叠多个存储器LSI和多个处理器LSI的半导体器件中，随着堆叠层数的增加，存储器LSI和处理器LSI之间的数据的通信距离将增加。 因此，用于通信的布线的寄生电容和寄生电阻增加，结果整个系统的功率和速度性能将降低。 堆叠处理器LSI 100和存储器LSI 200的组合中的至少两个或更多个，并且相同组合的处理器LSI 100和存储器LSI 200在垂直方向上彼此相邻堆叠。 通过设置在其间的专用电极来执行处理器LSI 100和存储器LSI 200之间的相同组合的通信，并且处理器LSI 100之间的通信以及从处理器LSI 100到外部的通信由用于信号11的贯穿硅通道 通过所有的LSI。

公开(公告)号：US20130079905A1

公开(公告)日：2013-03-28

申请号：US13701391

申请日：2010-06-03

申请人： Makoto Saen ,  Kiyoto Ito

发明人： Makoto Saen ,  Kiyoto Ito

IPC分类号： G05B15/02

CPC分类号： G05B15/02 ,  B25J9/1671 ,  B25J9/1689 ,  G05B2219/35464 ,  G05B2219/40168 ,  G05B2219/40625

摘要： In a human-operated working machine system made up of a working machine including an actuator and an operating device, various operations for target objects having various hardnesses and shapes are achieved at a speed not giving stress to an operator. To this end, the working machine has a control structure in which a control program corresponding to an action content is executed with both of displacement information with respect to the working machine inputted from the operating device and information from a sensor of the working machine being taken as inputs. Furthermore, the operating device has a simulator that predicts an action of the working machine so as to quickly provide image information and tactile information regarding the action of the working machine to the operator.

摘要翻译： 在由包括致动器和操作装置的作业机构构成的人造作业机械系统中，以对操作者不施加压力的速度实现具有各种硬度和形状的目标物体的各种操作。 为此，作业机械具有控制结构，在该控制结构中，对与动作内容相对应的控制程序，相对于从操作装置输入的作业机械的位移信息和来自作业机械的传感器的信息 作为输入。 此外，操作装置具有预测作业机械的作用的模拟器，以便快速地向操作者提供关于作业机械的动作的图像信息和触觉信息。

公开(公告)号：US08242589B2

公开(公告)日：2012-08-14

申请号：US13148993

申请日：2009-02-27

申请人： Makoto Saen ,  Kenichi Osada ,  Kiyoto Ito

发明人： Makoto Saen ,  Kenichi Osada ,  Kiyoto Ito

IPC分类号： H01L23/02

CPC分类号： G01R31/318513 ,  G11C5/04 ,  G11C29/02 ,  G11C29/025 ,  H01L2224/16145 ,  H01L2224/16225

摘要： In a test method of stacked LSIs connected by Through Silicon Vias, it is difficult to perform a failure diagnosis by using a conventional device test method to only one side of a silicon wafer, there is a possibility of yield degradation at a stacking time of LSIs, and a plurality of LSIs is connected to one Through Silicon Via so that it is necessary to select and remedy a defective Through Silicon Via taking into account all the device states. These problems cannot be solved by conventional test methods. Therefore, for a device test of a Through Silicon Via through a plurality of chips, a circuit that generates a time-series test pattern having both 0 and 1 values for a delay fault test is added to a circuit portion that transmits data to a Through Silicon Via in the stacked LSIs, and a circuit that receives the test pattern and compares the pattern received with a fixed pattern for a match to detect a defect of a Through Silicon Via is added to a circuit portion that receives data from a Through Silicon Via in the stacked LSIs.

摘要翻译： 在通过硅通孔连接的层叠LSI的测试方法中，仅通过使用传统的器件测试方法仅对硅晶片的一侧进行故障诊断是困难的，因此在LSI的堆叠时间内产生劣化的可能性 ，并且多个LSI连接到一个通硅通孔，使得有必要考虑到所有器件状态来选择和补救有缺陷的Through Silicon Via。 这些问题不能用传统的测试方法来解决。 因此，对于通过多个芯片的通孔硅器件的器件测试，产生用于延迟故障测试的具有0和1值的时间序列测试图案的电路被添加到电路部分，该电路部分将数据发送到通 在层叠的LSI中的硅通孔，以及接收测试图案并将接收的模式与用于匹配的固定模式进行比较以检测通硅通孔的缺陷的电路被添加到从直通硅通道接收数据的电路部分 在堆叠的LSI中。

公开(公告)号：US07977781B2

公开(公告)日：2011-07-12

申请号：US12916503

申请日：2010-10-30

申请人： Kiyoto Ito ,  Makoto Saen ,  Yuki Kuroda

发明人： Kiyoto Ito ,  Makoto Saen ,  Yuki Kuroda

IPC分类号： H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/063 ,  H01L23/544 ,  H01L23/552 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2224/0554 ,  H01L2224/05571 ,  H01L2224/16145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction. Communication between the processor LSI 100 and the memory LSI 200 in the same combination is performed by a dedicated electrode provided therebetween, and communication between processor LSIs 100 and communication from the processor LSI 100 to the outside are performed by a through silicon via for signal 11 which passes through all the LSIs.

摘要翻译： 在堆叠多个存储器LSI和多个处理器LSI的半导体器件中，随着堆叠层数的增加，存储器LSI和处理器LSI之间的数据的通信距离将增加。 因此，用于通信的布线的寄生电容和寄生电阻增加，结果整个系统的功率和速度性能将降低。 堆叠处理器LSI 100和存储器LSI 200的组合中的至少两个或更多个，并且相同组合的处理器LSI 100和存储器LSI 200在垂直方向上彼此相邻堆叠。 通过设置在其间的专用电极来执行处理器LSI 100和存储器LSI 200之间的相同组合的通信，并且处理器LSI 100之间的通信以及从处理器LSI 100到外部的通信由用于信号11的贯穿硅通道 通过所有的LSI。

公开(公告)号：US20100078790A1

公开(公告)日：2010-04-01

申请号：US12466018

申请日：2009-05-14

申请人： Kiyoto ITO ,  Makoto Saen ,  Yuki Kuroda

发明人： Kiyoto ITO ,  Makoto Saen ,  Yuki Kuroda

IPC分类号： H01L25/16 ,  H01L23/538

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/063 ,  H01L23/544 ,  H01L23/552 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2224/0554 ,  H01L2224/05571 ,  H01L2224/16145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction. Communication between the processor LSI 100 and the memory LSI 200 in the same combination is performed by a dedicated electrode provided therebetween, and communication between processor LSIs 100 and communication from the processor LSI 100 to the outside are performed by a through silicon via for signal 11 which passes through all the LSIs.

摘要翻译： 在堆叠多个存储器LSI和多个处理器LSI的半导体器件中，随着堆叠层数的增加，存储器LSI和处理器LSI之间的数据的通信距离将增加。 因此，用于通信的布线的寄生电容和寄生电阻增加，结果整个系统的功率和速度性能将降低。 堆叠处理器LSI 100和存储器LSI 200的组合中的至少两个或更多个，并且相同组合的处理器LSI 100和存储器LSI 200在垂直方向上彼此相邻堆叠。 通过设置在其间的专用电极来执行处理器LSI 100和存储器LSI 200之间的相同组合的通信，并且处理器LSI 100之间的通信以及从处理器LSI 100到外部的通信由用于信号11的贯穿硅通道 通过所有的LSI。