摘要:
A processor provides memory request and a coherency state value for a coherency granule associated with a memory request. The processor further provides either a first indicator or a second indicator depending on whether the coherency state value represents a cumulative coherency state for a plurality of caches of the processor. The first indicator and the second indicator identify the coherency state value as representing a cumulative coherency state or a potentially non-cumulative coherency state, respectively. If the second indicator is provided, a transaction management module determines whether to request the cumulative coherency state for the coherency granule in response to receiving the second indicator. The transaction management module then provides an indicator of the request for the cumulative coherency state to the processor in response to determining to request the cumulative coherency state. Otherwise, the transaction management module processes the memory transaction without requesting the cumulative coherency state.
摘要:
A processor provides memory request and a coherency state value for a coherency granule associated with a memory request. The processor further provides either a first indicator or a second indicator depending on whether the coherency state value represents a cumulative coherency state for a plurality of caches of the processor. The first indicator and the second indicator identify the coherency state value as representing a cumulative coherency state or a potentially non-cumulative coherency state, respectively. If the second indicator is provided, a transaction management module determines whether to request the cumulative coherency state for the coherency granule in response to receiving the second indicator. The transaction management module then provides an indicator of the request for the cumulative coherency state to the processor in response to determining to request the cumulative coherency state. Otherwise, the transaction management module processes the memory transaction without requesting the cumulative coherency state.
摘要:
A method includes communicating a first message between processors of a multiprocessor system via a coherency interconnect, whereby the first message includes coherency information. The method further includes communicating a second message between processors of the multiprocessor system via the coherency interconnect, whereby the second message includes interprocessor message information. A system includes a coherency interconnect and a processor. The processor includes an interface configured to receive messages from the coherency interconnect, each message including one of coherency information or interprocessor message information. The processor further includes a coherency management module configured to process coherency information obtained from at least one of the messages and an interrupt controller configured to generate an interrupt based on interprocessor message information obtained from at least one of the messages.
摘要:
A method includes communicating a first message between processors of a multiprocessor system via a coherency interconnect, whereby the first message includes coherency information. The method further includes communicating a second message between processors of the multiprocessor system via the coherency interconnect, whereby the second message includes interprocessor message information. A system includes a coherency interconnect and a processor. The processor includes an interface configured to receive messages from the coherency interconnect, each message including one of coherency information or interprocessor message information. The processor further includes a coherency management module configured to process coherency information obtained from at least one of the messages and an interrupt controller configured to generate an interrupt based on interprocessor message information obtained from at least one of the messages.
摘要:
A processing system includes a plurality of coherency domains and a plurality of coherency agents. Each coherency agent is associated with at least one of the plurality of coherency domains. At a select coherency agent of the plurality of coherency agents, an address translation for a coherency message is performed using a first memory address to generate a second memory address. A select coherency domain of the plurality of coherency domains associated with the coherency message is determined at the select coherency agent based on the address translation. The coherency message and a coherency domain identifier of the select coherency domain are provided by the select coherency agent to a coherency interconnect for distribution to at least one of the plurality of coherency agents based on the coherency domain identifier.
摘要:
A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings.
摘要:
In a data processing system, a marked bit is used to identify a data access instruction throughout the pipeline to indicate that the instruction meets user-specified criteria (e.g., a meets a data address range of interest). Based on the marked bit, an in-order program correlation message is generated which indicates when the data access instruction occurs relative to the instruction stream. The marked bit is also used to generate an in-order data trace message. As a result, the trace streams including only data access instructions meeting user-specified criteria may be post-processed and correlated precisely.
摘要:
A method and device for locking a cache line of a cache is disclosed. The method includes automatically changing a state of a cache line from a valid locked state to an invalid locked state in response to receiving an indication that a memory location external to the cache and corresponding to the cache line is associated with an access request by a processor or other data access module. Thus, the locked state of a cache line is maintained even after data in the locked cache line is invalidated. By maintaining the invalid locked state, the cache line is not available for reallocation by the cache. This allows locked cache lines that become invalidated to remain locked without additional software overhead to periodically determine whether the lock has been lost due to invalidation of the cache line.
摘要:
A technique for scheduling execution of threads at a processor is disclosed. The technique includes executing a thread de-emphasis instruction of a thread that de-emphasizes the thread until the number of pending memory transactions, such as cache misses, associated with the thread are at or below a threshold. While the thread is de-emphasized, other threads at the processor that have a higher priority can be executed or assigned system resources. Accordingly, the likelihood of a stall in the processor is reduced.
摘要:
In a data processing system, a marked bit is used to identify a data access instruction throughout the pipeline to indicate that the instruction meets user-specified criteria (e.g., a meets a data address range of interest). Based on the marked bit, an in-order program correlation message is generated which indicates when the data access instruction occurs relative to the instruction stream. The marked bit is also used to generate an in-order data trace message. As a result, the trace streams including only data access instructions meeting user-specified criteria may be post-processed and correlated precisely.