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    CBRAM cell with a reversible conductive bridging mechanism
    2.
    发明申请
    CBRAM cell with a reversible conductive bridging mechanism 审中-公开
    具有可逆导电桥接机构的CBRAM单元

    公开(公告)号：US20070274120A1

    公开(公告)日：2007-11-29

    申请号：US11051483

    申请日：2005-02-07

    申请人： Cay-Uwe Pinnow ,  Klaus Ufert ,  Michael Kund

    发明人： Cay-Uwe Pinnow ,  Klaus Ufert ,  Michael Kund

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0011 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1641

    摘要： According to the invention CBRAM cell is provided exhibiting a resistive switching effect offering the possibility to store multiple memory states in one cell by programming said memory cell to different resistance levels including at least a first memory state with a high resistance level representing a low-conductivity state of the memory cell and one memory state with a low resistance level representing a high-conductivity state of the memory cell, wherein the resistive switching effect is substantially based on a variation of the concentration of the metallic material incorporated or deposited in the matrix host material.

    摘要翻译： 根据本发明，提供具有电阻切换效果的CBRAM单元，其提供通过将所述存储器单元编程为不同的电阻电平来存储多个存储器状态的可能性，所述电阻级别至少包括表示低电导率的高电阻电平的第一存储器状态 存储单元的状态和表示存储单元的高导电性状态的低电阻水平的一个存储器状态，其中电阻切换效应基本上基于结合或沉积在矩阵主体中的金属材料的浓度的变化 材料。

    Method for manufacturing resistively switching memory devices
    3.
    发明申请
    Method for manufacturing resistively switching memory devices 失效
    用于制造电阻式切换存储器件的方法

    公开(公告)号：US20050250281A1

    公开(公告)日：2005-11-10

    申请号：US11113332

    申请日：2005-04-25

    申请人： Klaus Ufert ,  Cay-Uwe Pinnow

    发明人： Klaus Ufert ,  Cay-Uwe Pinnow

    IPC分类号： G11C13/02 ,  H01L21/336 ,  H01L21/8239 ,  H01L27/24 ,  H01L45/00

    CPC分类号： G11C13/0011 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1658 ,  H01L45/1675

    摘要： The present invention relates to a reproducible conditioning during the manufacturing of a resistively switching CBRAM memory cell comprising a first electrode and a second electrode with an active material positioned therebetween. The active material is adapted to be placed in a more or less electroconductive state by means of electrochemical switching processes. A CBRAM memory cell manufactured pursuant to the method according to the invention has, due to the improved conditioning, more reliable and more distinctly evaluable electrical switching properties. Moreover, no more forming step is necessary with the method according to the present invention.

    摘要翻译： 本发明涉及在制造电阻切换CBRAM存储单元期间的可再现调节，其包括第一电极和位于其间的活性材料的第二电极。 活性材料适于通过电化学切换工艺置于或多或少的导电状态。 根据本发明的方法制造的CBRAM存储单元由于改进的调理，具有更可靠和更明显的可评估电开关特性。 此外，根据本发明的方法不需要更多的成型步骤。

    Sub-lithographic structures, devices including such structures, and methods for producing the same
    4.
    发明申请
    Sub-lithographic structures, devices including such structures, and methods for producing the same 有权
    亚光刻结构，包括这种结构的装置及其制造方法

    公开(公告)号：US20060091476A1

    公开(公告)日：2006-05-04

    申请号：US11258367

    申请日：2005-10-26

    申请人： Cay-Uwe Pinnow ,  Thomas Happ ,  Michael Kund ,  Gerhard Mueller

    发明人： Cay-Uwe Pinnow ,  Thomas Happ ,  Michael Kund ,  Gerhard Mueller

    IPC分类号： H01L29/76 ,  H01L23/48 ,  H01L23/52 ,  H01L29/00

    CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76804 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method which makes it possible to define in a patterning layer openings having a first dimension that is substantially less than the feature size that can be obtained lithographically includes applying a sacrificial layer made of a material that is different from that of the patterning layer in a predetermined layer thickness on the patterning layer. Afterward, a photoresist layer is applied on the surface of the sacrificial layer, and an opening having a second dimension is defined lithographically in the photoresist layer. Afterward, an etching angle is set in a manner dependent on the layer thickness of the sacrificial layer and also the first and second dimensions, and the sacrificial layer is etched at the etching angle set. Afterward, the patterning layer is etched, the sacrificial layer is removed and a filling material is introduced into the opening produced in the patterning layer.

    摘要翻译： 可以在图案化层中限定具有基本上小于可以光刻获得的特征尺寸的第一尺寸的开口的方法，包括将由不同于图案形成层的材料制成的牺牲层 图案化层上的预定层厚度。 之后，在牺牲层的表面上施加光致抗蚀剂层，并且在光致抗蚀剂层中光刻地限定具有第二尺寸的开口。 之后，以取决于牺牲层的层厚度以及第一和第二尺寸的方式设置蚀刻角度，并且以蚀刻角度设置蚀刻牺牲层。 之后，蚀刻图形层，去除牺牲层，并将填充材料引入图案化层中产生的开口中。

    Intergrated semiconductor memory and method for producing an integrated semiconductor memory
    5.
    发明申请
    Intergrated semiconductor memory and method for producing an integrated semiconductor memory 有权
    集成半导体存储器和集成半导体存储器的制造方法

    公开(公告)号：US20060291268A1

    公开(公告)日：2006-12-28

    申请号：US11441805

    申请日：2006-05-26

    申请人： Thomas Happ ,  Cay-Uwe Pinnow ,  Ralf Symanczyk ,  Klaus-Dieter Ufert

    发明人： Thomas Happ ,  Cay-Uwe Pinnow ,  Ralf Symanczyk ,  Klaus-Dieter Ufert

    IPC分类号： G11C17/00

    CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/1666

    摘要： An integrated semiconductor memory includes a storage medium (6) arranged between two electrodes (10, 20), which storage medium may be a phase change medium, for example. The storage medium (6) can be put into a first state or a second state by means of an electric current, as a result of which an item of information can be stored. According to embodiments of the invention, a layer plane (L) is provided in which impurity particles made from a material (4) are embedded, as a result of which the current density in the storage medium is locally increased and the programming current required for reprogramming is reduced. As a result, the current consumption of memory elements containing a phase change medium is reduced, so that for the first time they can be embodied with minimal feature size, together with other components such as transistors, and integrated into a single semiconductor circuit and no longer have to be arranged in separate subcircuits.

    摘要翻译： 集成半导体存储器包括布置在两个电极（10,20）之间的存储介质（6），该存储介质可以是例如相变介质。 存储介质（6）可以通过电流进入第一状态或第二状态，结果可以存储信息项。 根据本发明的实施例，提供了一种层状平面（L），其中嵌入由材料（4）制成的杂质颗粒，结果存储介质中的电流密度局部增加，并且需要编程电流 重编程减少。 结果，包含相变介质的存储元件的电流消耗减少，使得它们可以首次以最小的特征尺寸与其他元件（例如晶体管）一体化，并且集成到单个半导体电路中，并且不存在 更长的时间必须在单独的子电路中排列。

    Reactive sputtering process for optimizing the thermal stability of thin chalcogenide layers
    7.
    发明申请
    Reactive sputtering process for optimizing the thermal stability of thin chalcogenide layers 失效
    用于优化薄硫族化物层的热稳定性的反应溅射工艺

    公开(公告)号：US20060043354A1

    公开(公告)日：2006-03-02

    申请号：US11214023

    申请日：2005-08-30

    申请人： Cay-Uwe Pinnow ,  Thomas Happ

    发明人： Cay-Uwe Pinnow ,  Thomas Happ

    IPC分类号： H01L29/02

    CPC分类号： C23C14/0623 ,  C23C16/305 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/143 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

    摘要： A chalcogenide layer includes a composition of compounds having the formula MmX1-m, where M denotes one or more elements selected from the group consisting of group IVb elements of the periodic system, group Vb elements of the periodic system and transition metals, X denotes one or more elements selected from the group consisting of S, Se and Te, and m has a value of between 0 and 1. The chalcogenide layer further includes an oxygen or nitrogen content in the range from 0.001 atomic % to 75 atomic %.

    摘要翻译： 硫族化物层包括具有式M 1 X 1-m的化合物的组合物，其中M表示一种或多种选自下组的IVb族元素： 周期性系统，Vb族元素和过渡金属，X表示选自S，Se和Te中的一种或多种元素，m具有0和1之间的值。硫族化物层还包括氧 或氮含量在0.001原子％至75原子％的范围内。

    Nonvolatile integrated semiconductor memory
    9.
    发明申请
    Nonvolatile integrated semiconductor memory 失效
    非易失性集成半导体存储器

    公开(公告)号：US20050067634A1

    公开(公告)日：2005-03-31

    申请号：US10950477

    申请日：2004-09-28

    申请人： Cay-Uwe Pinnow ,  Martin Gutsche ,  Harald Seidl ,  Thomas Happ

    发明人： Cay-Uwe Pinnow ,  Martin Gutsche ,  Harald Seidl ,  Thomas Happ

    IPC分类号： G03G15/02 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

    CPC分类号： H01L21/28282 ,  H01L29/42332 ,  H01L29/7881 ,  Y10S438/954

    摘要： A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.

    摘要翻译： 非易失性集成半导体存储器具有具有隧道势垒层和电荷存储电平的层的排列。 电荷储存电平具有在空间固定位置中分散存储在电荷载体中的电介质材料。 隧道势垒层具有高能电荷载流子穿过的材料。 电荷存储水平的至少一个界面表面具有比远离电荷存储水平的隧道势垒层的界面更大的微观粗糙度。 电荷存储水平在第一区域中具有比在第二区域中更大的层厚度。 这在横向方向产生正电荷载体和负电荷载体的相对相同的分布和定位。 因此，分散到电荷存储电平的电荷载体完全复合，从而降低了在非易失性存储器的长期操作期间不可预见的数据丢失的风险。

    Reactive sputtering process for optimizing the thermal stability of thin chalcogenide layers
    10.
    发明授权
    Reactive sputtering process for optimizing the thermal stability of thin chalcogenide layers 失效
    用于优化薄硫族化物层的热稳定性的反应溅射工艺

    公开(公告)号：US07692175B2

    公开(公告)日：2010-04-06

    申请号：US11214023

    申请日：2005-08-30

    申请人： Cay-Uwe Pinnow ,  Thomas Happ

    发明人： Cay-Uwe Pinnow ,  Thomas Happ

    IPC分类号： H01L29/02

    CPC分类号： C23C14/0623 ,  C23C16/305 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/143 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

    摘要： A chalcogenide layer includes a composition of compounds having the formula MmX1-m, where M denotes one or more elements selected from the group consisting of group IVb elements of the periodic system, group Vb elements of the periodic system and transition metals, X denotes one or more elements selected from the group consisting of S, Se and Te, and m has a value of between 0 and 1. The chalcogenide layer further includes an oxygen or nitrogen content in the range from 0.001 atomic % to 75 atomic %.

    摘要翻译： 硫族化物层包括具有式MmX1-m的化合物的组合物，其中M表示选自周期系统的IVb族元素，周期系中的Vb族元素和过渡金属的一种或多种元素，X表示一种 或更多选自S，Se和Te的元素，并且m具有0和1之间的值。硫族化物层还包括0.001原子％至75原子％范围内的氧或氮含量。