公开(公告)号：US5761109A

公开(公告)日：1998-06-02

申请号：US614537

申请日：1996-03-13

申请人： Daisaburo Takashima ,  Tsuneo Inaba ,  Yukihito Oowaki ,  Takashi Ohsawa ,  Shinichiro Shiratake

发明人： Daisaburo Takashima ,  Tsuneo Inaba ,  Yukihito Oowaki ,  Takashi Ohsawa ,  Shinichiro Shiratake

IPC分类号： G11C11/409 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/06

CPC分类号： G11C11/4097

摘要： A dynamic semiconductor memory device according to the present invention comprises at least first and second memory cell arrays having a plurality of memory cells selectively arranged at respective intersections of a plurality of word lines and a plurality of bit lines, a first sense amplifier section connected at an end of the first cell array to a plurality of bit line pairs formed by part of the plurality of bit lines of the first cell array, the plurality of bit line pairs having a folded bit line configuration, a second sense amplifier section connected to sets of bit line pairs, each formed by one of the remaining bit lines of the first cell array and one of part of the plurality of bit lines of the second cell array, the plurality of bit line pairs having an open bit line configuration, and a correction circuit for correcting the level of ease for reading data "0" and that of reading data "1".

摘要翻译： 根据本发明的动态半导体存储器件包括至少第一和第二存储器单元阵列，其具有选择性地布置在多个字线和多个位线的各个交点处的多个存储器单元，第一读出放大器部分连接在 第一单元阵列的一端到由第一单元阵列的多个位线的一部分形成的多个位线对，多个位线对具有折叠位线配置，第二读出放大器部分连接到组 的位线对，每个位线对由第一单元阵列的剩余位线之一和第二单元阵列的多个位线的一部分之一形成，多个位线对具有打开的位线配置，以及 用于校正读取数据“0”的容易程度的校正电路和读取数据“1”的校正电路。

公开(公告)号：US06993691B2

公开(公告)日：2006-01-31

申请号：US10120146

申请日：2002-04-11

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Yukihito Oowaki ,  Katsuhiko Hoya ,  Takeshi Watanabe

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Yukihito Oowaki ,  Katsuhiko Hoya ,  Takeshi Watanabe

IPC分类号： G11C29/00

CPC分类号： G11C8/08 ,  G11C11/22

摘要： Potential of a word line connected to any selected one of memory cells is lowered and potential of word lines connected to non-selected memory cells are raised. The potential of the plate line is raised and lowered. The potential of the bit line is raised and lowered. After this, reading data from the memory cells after potential raising and lowering of the plate line and potential raising and lowering of the bit line have been alternately performed at least one time, thereby to determine attenuation of polarization in the ferroelectric capacitor.

公开(公告)号：US5969998A

公开(公告)日：1999-10-19

申请号：US213773

申请日：1998-12-17

申请人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

发明人： Yukihito Oowaki ,  Daisuke Kato ,  Daisaburo Takashima

IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00 ,  G11C11/24

CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C7/065

摘要： A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode coupled to a word line and being connected between the capacitor and a bit line. Sense amplifier circuits are connected to the bit line pairs, and have a first and a second common source line. A decoder and a word line driver are connected to the word lines. A MOS transistor is connected between the power supply voltage and the first common source line, for selectively supplying it with a first voltage which potentially defines a high-level voltage for the bit line pairs. A voltage generator is connected through a MOS transistor to the second common source line, for generating a second voltage which potentially defines a low-level voltage for the bit line pairs, and which is selectively supplied to the second common source line. The second voltage is greater in potential than the ground potential, which is employed as a source voltage.

公开(公告)号：US07236035B2

公开(公告)日：2007-06-26

申请号：US10990537

申请日：2004-11-18

申请人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara

发明人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara

IPC分类号： G06F1/04

CPC分类号： G06F1/10

摘要： A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.

摘要翻译： 第一个逻辑电路的电源电压被控制。 第二逻辑电路响应于外部时钟信号而工作。 调整电路包括提供有外部时钟信号的第一延迟电路和检测电路，其检测从第一逻辑电路输出的第一时钟信号的定时与从第二逻辑电路部分输出的第二时钟信号之间的偏差。 调整电路根据检测电路的检测结果来调整第一延迟电路的延迟时间，并将第一延迟电路的输出信号作为第三时钟信号施加到第一逻辑电路。

公开(公告)号：US07057917B2

公开(公告)日：2006-06-06

申请号：US10743906

申请日：2003-12-24

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

摘要翻译： 链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线 通过开关晶体管，放大该位线及其互补位线的电压的读出放大器，以及插在开关晶体管和读出放大器之间的晶体管。 作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值 电压和比较放大。 利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

公开(公告)号：US5838038A

公开(公告)日：1998-11-17

申请号：US478620

申请日：1995-06-07

申请人： Daisaburo Takashima ,  Shigeyoshi Watanabe ,  Tohru Ozaki ,  Takeshi Hamamoto ,  Yukihito Oowaki

发明人： Daisaburo Takashima ,  Shigeyoshi Watanabe ,  Tohru Ozaki ,  Takeshi Hamamoto ,  Yukihito Oowaki

IPC分类号： G11C7/18 ,  H01L27/108

CPC分类号： G11C7/18 ,  G11C2211/4013

摘要： A semiconductor memory device includes active regions arranged on a semiconductor substrate such that those of the active regions which are adjacent in the word line direction deviate in the bit line direction, MOS transistors respectively formed in the active regions and each having a source and a drain one of which is connected to the bit line, a plurality of trenches each arranged to another set of source an drain regions and arranged to deviate in the word line direction in the respective active regions, those of the trenches which are adjacent with a through word line disposed therebetween being arranged to deviate in the bit line direction so as to be set closer to each other, a plurality of storage electrodes respectively formed in the trenches with capacitor insulative films disposed therebetween, and connection electrodes arranged between the word lines and each connecting the other of the source and drain to the storage electrode.

摘要翻译： 半导体存储器件包括布置在半导体衬底上的有源区域，使得在字线方向上相邻的有源区域在位线方向偏离的有源区域分别形成在有源区域中并且各自具有源极和漏极 其中一个连接到位线，多个沟槽，每个沟槽被布置成另一组源极漏极区域，并且被布置成在相应的有源区域中的字线方向偏离，与通过字相邻的沟槽的那些沟槽 配置在它们之间的线被布置为在位线方向上偏离以使得彼此更靠近，分别形成在沟槽中的多个存储电极，其中设置有电容器绝缘膜，以及布置在字线和每个连接之间的连接电极 另一个源极和漏极到存储电极。

公开(公告)号：US5499209A

公开(公告)日：1996-03-12

申请号：US457738

申请日：1995-06-01

申请人： Yukihito Oowaki ,  Daisaburo Takashima ,  Masako Ohta

发明人： Yukihito Oowaki ,  Daisaburo Takashima ,  Masako Ohta

IPC分类号： G11C11/407 ,  G11C11/408 ,  G11C7/00 ,  H03K17/687

CPC分类号： G11C11/4085

摘要： A word-line drive voltage generation circuit for use in a dynamic random-access memory is disclosed which is connected to a word line via a row decoder including MOS transistors. The circuit includes a charge-bootstrap capacitor having insulated electrodes, one of which is connected to a first reference voltage generator via a switching MOS transistor, and the other of which is connected via a MOS transistor to a second reference voltage generator. These voltage generators provide the capacitor with the constant d.c. voltage that are essentially insensitive to variation in the power supply voltage for the memory. The resultant word-line drive voltage may thus be free from variation in the power supply voltage during the operation modes of the memory. This enables the word-line voltage to be high enough to allow successful "H" level writing at a selected memory cell without creation of any unwantedly increased dielectric breakdown therein, in the entire allowable range of the power supply voltage.

摘要翻译： 公开了一种用于动态随机存取存储器的字线驱动电压产生电路，其通过包括MOS晶体管的行解码器连接到字线。 该电路包括具有绝缘电极的电荷自举电容器，其中一个经由开关MOS晶体管连接到第一参考电压发生器，另一个经由MOS晶体管连接到第二参考电压发生器。 这些电压发生器为电容器提供恒定的直流电压。 对于存储器的电源电压的变化基本上不敏感的电压。 因此，在存储器的操作模式期间，所得到的字线驱动电压可能没有电源电压的变化。 这使得字线电压足够高，以允许在所选择的存储器单元中成功地“H”电平写入，而不会在电源电压的整个允许范围内产生不必要的增加的电介质击穿。

公开(公告)号：US5084842A

公开(公告)日：1992-01-28

申请号：US536718

申请日：1990-06-12

申请人： Kenji Tsuchida ,  Yukihito Oowaki ,  Daisaburo Takashima

发明人： Kenji Tsuchida ,  Yukihito Oowaki ,  Daisaburo Takashima

IPC分类号： G11C11/409 ,  G11C11/401 ,  G11C11/4091 ,  G11C11/4094 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10805 ,  G11C11/4091 ,  G11C11/4094

摘要： A dynamic random access memory has a substrate, plural pairs of parallel bit lines provided on the substrate, parallel word lines insulatively crossing the parallel bit lines to define cross points therebetween, and memory cells provided at the cross points. Each memory cell has a data storage capacitor and a transistor. Sense amplifiers are provided at bit line pairs, respectively, to sense a data voltage. A discharge control section, which is associated with the sense amplifiers, forms discharge paths branched between the bit line pairs and the substrate grounded to progress the discharging of charges, when a certain word line is designated and a memory cell is selected from those memory cells which are connected to the certain word line, whereby the operational speed of the memory is increased.

摘要翻译： 动态随机存取存储器具有衬底，设置在衬底上的多对并行位线，并行字线绝对地穿过并行位线以限定它们之间的交叉点，以及设置在交叉点处的存储单元。 每个存储单元具有数据存储电容器和晶体管。 分别在位线对处提供感测放大器以感测数据电压。 与读出放大器相关联的放电控制部分在指定某个字线并且从那些存储器单元中选择存储器单元时，形成在位线对和衬底之间分支的放电路径，从而导致电荷的放电 其连接到某个字线，由此增加存储器的操作速度。

公开(公告)号：US5062077A

公开(公告)日：1991-10-29

申请号：US556470

申请日：1990-07-24

申请人： Daisaburo Takashima ,  Yukihito Oowaki ,  Kenji Tsuchida

发明人： Daisaburo Takashima ,  Yukihito Oowaki ,  Kenji Tsuchida

IPC分类号： G11C7/02 ,  G11C7/18 ,  G11C11/4097 ,  H01L27/108

CPC分类号： G11C7/18 ,  G11C11/4097 ,  H01L27/10805

摘要： A dynamic-type semiconductor memory device comprises bit lines, every two bit lines forming a folded bit line pair, every two pairs forming a bit-line unit such that one of the bit lines of the first pair extends between the bit lines of the second pair, and the bit lines of the second pair are twisted at middle portion, word lines intersecting with the bit lines, dummy word lines, extending parallel to the word lines, two of the dummy word lines being arranged on one side of the crossing portions of the bit lines of the second pair, and the other two of the dummy word lines being arranged on the other side of the crossing portions of the bit lines of the second pair, memory cells connected to selected ones of the intersections of the bit lines and the word lines, such that any adjacent memory cells connected to the same word line form a group which is arranged every two bit lines, and any adjacent two memory cells connected to the same bit line are shifted by half-pitch distance with respect to the corresponding two adjacent memory cells connected to either adjacent bit line, a plurality of dummy cells connected to selected ones of the intersections of the bit lines and the word lines, such that at least one dummy cell is connected to each bit line, and sense amplifiers provided for the pairs of bit lines, respectively.

摘要翻译： 动态型半导体存储器件包括位线，每两条位线形成折叠位线对，每两对形成位线单元，使得第一对的位线中的一条在第二对的位线之间延伸 并且第二对的位线在中间部分被扭曲，与位线相交的字线，与字线平行延伸的虚拟字线，两个虚拟字线被布置在交叉部分的一侧 并且另外两个虚拟字线被布置在第二对的位线的交叉部分的另一侧上，连接到位线的所选交叉点中的所选位置的存储器单元 和字线，使得连接到相同字线的任何相邻的存储单元形成每两位排布置的组，并且连接到同一位线的任何相邻的两个存储单元偏移半间距距离， 相对于连接到相邻位线的相应的两个相邻存储单元，连接到位线和字线的所选交叉的多个虚拟单元，使得至少一个虚设单元连接到每个位线， 以及分别为位线对提供的读出放大器。

公开(公告)号：US20060271799A1

公开(公告)日：2006-11-30

申请号：US11216018

申请日：2005-09-01

申请人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

发明人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

IPC分类号： G06F1/26

CPC分类号： G06F1/26 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

摘要： According to the present invention, there is provided a semiconductor device comprising: a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level, wherein said power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号 电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平，其中所述电源电路基于施加到其的第二控制信号输出具有第二电平的内部电源电压 。