公开(公告)号：US20050155001A1

公开(公告)日：2005-07-14

申请号：US10988658

申请日：2004-11-16

申请人： Koichi Kinoshita ,  Takeshi Ishigaki ,  Yukihiro Urakawa

发明人： Koichi Kinoshita ,  Takeshi Ishigaki ,  Yukihiro Urakawa

IPC分类号： G06F17/50 ,  H01L21/82

CPC分类号： G06F17/5045

摘要： A method for designing a semiconductor integrated circuit, includes placing first, second and third cells, respectively including first stage synchronous circuit having signal propagation time, second stage synchronous circuit having a signal propagation time almost equal to the first stage synchronous circuit, and logic circuit; routing wirings so as to electrically connect the first to third cells; verifying signal propagation timing of the semiconductor integrated circuit having the first to third cells; adjusting the signal propagation timing based on critical path of the signal propagation timing of the semiconductor integrated circuit; and extracting the critical path to replace the second stage synchronous circuit by synchronous circuit of different synchronous type from the first stage synchronous circuit so as to provide a shorter signal propagation time than the first stage synchronous circuit.

摘要翻译： 一种用于设计半导体集成电路的方法，包括分别包括具有信号传播时间的第一级同步电路的第一，第二和第三单元，具有几乎等于第一级同步电路的信号传播时间的第二级同步电路和逻辑电路 ; 路由布线以便电连接第一至第三单元; 验证具有第一至第三小区的半导体集成电路的信号传播定时; 基于半导体集成电路的信号传播定时的关键路径调整信号传播定时; 并通过与第一级同步电路不同同步型的同步电路提取替代第二级同步电路的关键路径，以提供比第一级同步电路更短的信号传播时间。

公开(公告)号：US07353481B2

公开(公告)日：2008-04-01

申请号：US11320643

申请日：2005-12-30

申请人： Koichi Kinoshita ,  Yukihiro Urakawa

发明人： Koichi Kinoshita ,  Yukihiro Urakawa

IPC分类号： G06F17/50 ,  H01L25/00 ,  H03L19/00 ,  H03H1/00 ,  H03H2/00

CPC分类号： G06F17/5068 ,  H01L23/522 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A computer implemented method for designing a semiconductor integrated circuit includes placing dummy pattern on a second interconnection layer positioned just above the first power line based on a placement result of the first power line, the dummy pattern having a long axis parallel with a direction of the first power line; and electrically connecting the dummy pattern to the first power line, based on placement results of the first power line and the dummy pattern.

摘要翻译： 一种用于设计半导体集成电路的计算机实现方法包括：基于第一电力线的放置结果，将伪图案放置在位于第一电力线正上方的第二互连层上，虚设图案具有与第一电力线的方向平行的长轴 第一电力线; 并且基于第一电力线和虚拟图案的配置结果，将虚设图案电连接到第一电力线。

公开(公告)号：US06859070B2

公开(公告)日：2005-02-22

申请号：US10389876

申请日：2003-03-18

申请人： Koichi Kinoshita ,  Yukihiro Urakawa

发明人： Koichi Kinoshita ,  Yukihiro Urakawa

IPC分类号： G11C19/00 ,  G01R31/3185 ,  G11C29/10 ,  H01L21/822 ,  H01L27/04 ,  H03K3/037 ,  H03K19/00 ,  G01R31/28

CPC分类号： G01R31/318583 ,  G01R31/318544 ,  H03K3/0375

摘要： A semiconductor integrated circuit device includes a plurality of flip-flops, each of which has an external input terminal and external output terminal, the flip-flops being cascade-connected by having data output terminals respectively connected to data input terminals of the next-stage flip-flops. A reset signal is input via the external input terminal of the first-stage flip-flop and is sequentially transferred from the external output terminal thereof to the next-stage flip-flops. The reset signal is transferred via a transmission path different from the original data transmission path to reset all of the flip-flops.

摘要翻译： 半导体集成电路器件包括多个触发器，每个触发器具有外部输入端和外部输出端，触发器通过分别连接到下一级的数据输入端的数据输出端级联连接 人字拖。 复位信号通过第一级触发器的外部输入端输入，并从其外部输出端依次传送到下一级触发器。 复位信号经由与原始数据传输路径不同的传输路径传送，以复位所有触发器。

公开(公告)号：US20060166434A1

公开(公告)日：2006-07-27

申请号：US11320643

申请日：2005-12-30

申请人： Koichi Kinoshita ,  Yukihiro Urakawa

发明人： Koichi Kinoshita ,  Yukihiro Urakawa

IPC分类号： H01L21/8242 ,  H01L23/48 ,  H01L23/52

CPC分类号： G06F17/5068 ,  H01L23/522 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A computer implemented method for designing a semiconductor integrated circuit includes placing dummy pattern on a second interconnection layer positioned just above the first power line based on a placement result of the first power line, the dummy pattern having a long axis parallel with a direction of the first power line; and electrically connecting the dummy pattern to the first power line, based on placement results of the first power line and the dummy pattern.

摘要翻译： 一种用于设计半导体集成电路的计算机实现方法包括：基于第一电力线的放置结果，将伪图案放置在位于第一电力线正上方的第二互连层上，虚设图案具有与第一电力线的方向平行的长轴 第一电力线; 并且基于第一电力线和虚拟图案的配置结果，将虚设图案电连接到第一电力线。

公开(公告)号：US09096508B2

公开(公告)日：2015-08-04

申请号：US14130132

申请日：2012-06-29

申请人： Kento Kanaya ,  Koichi Kinoshita ,  Masaru Hirano

发明人： Kento Kanaya ,  Koichi Kinoshita ,  Masaru Hirano

IPC分类号： C12R1/645 ,  C12P23/00 ,  C07C45/78 ,  C07C403/24 ,  A61K31/122 ,  A61K31/575 ,  A61K36/07

CPC分类号： C07C45/78 ,  A61K31/122 ,  A61K31/575 ,  A61K36/07 ,  C07C403/24 ,  C07C2601/14 ,  C12P23/00

摘要： The present invention provides an efficient method for industrially producing a naturally-derived carotenoid composition with a large amount of a carotenoid such as astaxanthin from a culture of a yeast of the genus Xanthophyllomyces without requiring any special extraction equipment and any complicated refinement process and without any need for organic solvents harmful to humans. Provided is a method for producing a carotenoid composition, including the steps of washing a carotenoid-containing yeast of the genus Xanthophyllomyces with an organic solvent (A) at 30° C. or lower, and extracting a carotenoid from the washed yeast with an organic solvent (B) at 10° C. to 70° C.

摘要翻译： 本发明提供一种有效的方法，用于工业生产具有大量类胡萝卜素的类胡萝卜素组合物，所述类胡萝卜素组合物具有大量的类胡萝卜素，如来自叶黄素属酵母的培养物中的虾青素，而不需要任何特殊的提取设备和任何复杂的精制过程， 需要对人体有害的有机溶剂。 本发明提供一种制备类胡萝卜素组合物的方法，包括以下步骤：用有机溶剂（A）在30℃或更低温度下清洗含有类胡萝卜素的酵母属的Xanthophyllomyces酵母，并用有机溶剂从洗涤的酵母中提取类胡萝卜素 溶剂（B）在10℃至70℃

公开(公告)号：US07936902B2

公开(公告)日：2011-05-03

申请号：US11667670

申请日：2004-11-12

申请人： Koichi Kinoshita

发明人： Koichi Kinoshita

IPC分类号： G06K9/00

CPC分类号： G06K9/00281 ,  G06T7/75 ,  G06T2207/30201

摘要： Plural nodes are arranged at predetermined initial positions, and feature values at plural sampling points around each node are obtained as a node feature value of each corresponding node. An error estimator indicating displacement between the current position of each node and the position of corresponding feature point is obtained based on correlation information on a difference between the node feature value obtained in a state in which the plural nodes are arranged at correct positions of the corresponding feature points and the node feature value obtained in a state in which the plural nodes are arranged at wrong positions of the corresponding feature points in a learning image, correlation information on a difference between the correct position and the wrong position, and a node feature value of each node. The position of each feature point is estimated in an input image based on the error estimator and the current position of each node.

摘要翻译： 多个节点被布置在预定的初始位置，并且获得每个节点周围多个采样点的特征值作为每个对应节点的节点特征值。 基于相关信息获得各个节点的当前位置与对应的特征点的位置之间的位移的误差估计器，该相关信息是在将多个节点布置在相应的位置的正确位置的状态下获得的节点特征值 特征点和在多个节点布置在学习图像中的相应特征点的错误位置的状态下获得的节点特征值，关于正确位置和错误位置之间的差异的相关信息以及节点特征值 的每个节点。 基于误差估计器和每个节点的当前位置，在输入图像中估计每个特征点的位置。

公开(公告)号：US20100270600A1

公开(公告)日：2010-10-28

申请号：US12728913

申请日：2010-03-22

申请人： Takashi Inukai ,  Koichi Kinoshita ,  Masato Kanie

发明人： Takashi Inukai ,  Koichi Kinoshita ,  Masato Kanie

IPC分类号： H01L29/78 ,  G06F17/50

CPC分类号： H01L27/0207 ,  G06F17/5031 ,  G06F17/5072 ,  G06F2217/12 ,  G06F2217/78 ,  G06F2217/84 ,  H01L27/11807 ,  Y02P90/265

摘要： A method of designing a semiconductor integrated circuit device includes: arranging standard cells constituting a MISFET; analyzing an operation timing and/or power consumption of the arranged standard cells; identifying one of the standard cells that is desired to have improved properties as a cell of interest based on the obtained analysis result; optimizing an arrangement and a shape of blank areas around the cell of interest taking into account an influence of a well proximity effect; and replacing the blank area and/or the cell of interest with a WPE-reduced or WPE-enhancing cell.

摘要翻译： 一种设计半导体集成电路器件的方法包括：布置构成MISFET的标准单元; 分析所配置的标准单元的操作定时和/或功耗; 基于获得的分析结果，鉴定期望具有改进的性质的标准细胞之一作为感兴趣的细胞; 考虑到井附近效应的影响，优化感兴趣细胞周围的空白区域的布置和形状; 并且用WPE还原或WPE增强细胞代替感兴趣的空白区域和/或细胞。

公开(公告)号：US07329938B2

公开(公告)日：2008-02-12

申请号：US10845247

申请日：2004-05-14

申请人： Koichi Kinoshita

发明人： Koichi Kinoshita

IPC分类号： H01L29/00

CPC分类号： H01L27/0207 ,  H01L27/11807

摘要： A semiconductor integrated circuit includes a first cell spanning one of the p-wells and one of the n-wells adjacent to each other, and having one end on a dividing line inside the p-well and another end on a dividing line inside the n-well, and having a height determined by the one end and the another end; and a second cell, spanning another one of the p-wells and another one of the n-wells adjacent to each other, with a height covering the entire widths of the p- and n-wells measured along the column direction, the height of the second cell is double that of the first cell.

摘要翻译： 一种半导体集成电路包括跨越p阱中的一个和彼此相邻的n个阱中的一个的第一单元，并且在p阱内部的分隔线上的一端和n阱内的分界线上的另一端 并且具有由一端和另一端确定的高度; 以及跨越另一个p阱和彼此相邻的n个阱中的另一个的第二单元，具有覆盖沿着列方向测量的p阱和n阱的整个宽度的高度， 第二个单元格是第一个单元格的两倍。

公开(公告)号：US20070013791A1

公开(公告)日：2007-01-18

申请号：US11477950

申请日：2006-06-30

申请人： Koichi Kinoshita ,  Shuichiro Tsukiji ,  Miki Matsuoka ,  Takayoshi Yamashita

发明人： Koichi Kinoshita ,  Shuichiro Tsukiji ,  Miki Matsuoka ,  Takayoshi Yamashita

IPC分类号： H04N5/262

CPC分类号： G01S3/7864

摘要： A tracking apparatus and method in which the possible position of a current face is estimated based on the face positions previously determined as well as plural pieces of ambient information corresponding to the possible positions obtained. The current face position is estimated based on the position of the ambient information that is most similar to the ambient information obtained from previous detections.

摘要翻译： 一种跟踪装置和方法，其中基于先前确定的面部位置以及与获得的可能位置相对应的多个环境信息来估计当前脸部的可能位置。 基于与从先前检测获得的环境信息最相似的环境信息的位置估计当前面部位置。

公开(公告)号：US20050228168A1

公开(公告)日：2005-10-13

申请号：US10992133

申请日：2004-11-19

申请人： Koichi Kinoshita ,  Fumio Osakada ,  Yasuyoshi Ueda ,  Karunakaran Narasimhan ,  Angella Cearley ,  Kenneth Yee ,  Isao Noda

发明人： Koichi Kinoshita ,  Fumio Osakada ,  Yasuyoshi Ueda ,  Karunakaran Narasimhan ,  Angella Cearley ,  Kenneth Yee ,  Isao Noda

IPC分类号： C08F6/00 ,  C08G63/06 ,  C08G63/90 ,  C12P7/62

CPC分类号： C12P7/625 ,  C08G63/06 ,  C08G63/90

摘要： The present invention provides a method for conveniently obtaining a biodegradable polyhydroxyalkanoate by a solvent extraction method. A method for producing a polyhydroxyalkanoate crystal comprises precipitating a polyhydroxyalkanoate crystal using a monohydric alcohol having 4 to 10 carbon atoms as a extraction solvent, keeping a polyhydroxyalkanoate solution containing 0.1 to 10% by weight of water relative to the total amount of the solution warm at 70° C. or higher, and cooling the solution to below 70° C.

摘要翻译： 本发明提供一种通过溶剂萃取方法方便地获得生物可降解的聚羟基链烷酸酯的方法。 聚羟基链烷酸酯晶体的制造方法包括使用具有4〜10个碳原子的一元醇作为提取溶剂使聚羟基链烷酸酯晶体析出，保持含有0.1〜10重量％的水的聚羟基链烷酸酯溶液相对于温度为 70℃以上，将溶液冷却至70℃以下。