公开(公告)号：US07353481B2

公开(公告)日：2008-04-01

申请号：US11320643

申请日：2005-12-30

申请人： Koichi Kinoshita ,  Yukihiro Urakawa

发明人： Koichi Kinoshita ,  Yukihiro Urakawa

IPC分类号： G06F17/50 ,  H01L25/00 ,  H03L19/00 ,  H03H1/00 ,  H03H2/00

CPC分类号： G06F17/5068 ,  H01L23/522 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A computer implemented method for designing a semiconductor integrated circuit includes placing dummy pattern on a second interconnection layer positioned just above the first power line based on a placement result of the first power line, the dummy pattern having a long axis parallel with a direction of the first power line; and electrically connecting the dummy pattern to the first power line, based on placement results of the first power line and the dummy pattern.

摘要翻译： 一种用于设计半导体集成电路的计算机实现方法包括：基于第一电力线的放置结果，将伪图案放置在位于第一电力线正上方的第二互连层上，虚设图案具有与第一电力线的方向平行的长轴 第一电力线; 并且基于第一电力线和虚拟图案的配置结果，将虚设图案电连接到第一电力线。

公开(公告)号：US06859070B2

公开(公告)日：2005-02-22

申请号：US10389876

申请日：2003-03-18

申请人： Koichi Kinoshita ,  Yukihiro Urakawa

发明人： Koichi Kinoshita ,  Yukihiro Urakawa

IPC分类号： G11C19/00 ,  G01R31/3185 ,  G11C29/10 ,  H01L21/822 ,  H01L27/04 ,  H03K3/037 ,  H03K19/00 ,  G01R31/28

CPC分类号： G01R31/318583 ,  G01R31/318544 ,  H03K3/0375

摘要： A semiconductor integrated circuit device includes a plurality of flip-flops, each of which has an external input terminal and external output terminal, the flip-flops being cascade-connected by having data output terminals respectively connected to data input terminals of the next-stage flip-flops. A reset signal is input via the external input terminal of the first-stage flip-flop and is sequentially transferred from the external output terminal thereof to the next-stage flip-flops. The reset signal is transferred via a transmission path different from the original data transmission path to reset all of the flip-flops.

摘要翻译： 半导体集成电路器件包括多个触发器，每个触发器具有外部输入端和外部输出端，触发器通过分别连接到下一级的数据输入端的数据输出端级联连接 人字拖。 复位信号通过第一级触发器的外部输入端输入，并从其外部输出端依次传送到下一级触发器。 复位信号经由与原始数据传输路径不同的传输路径传送，以复位所有触发器。

公开(公告)号：US20050155001A1

公开(公告)日：2005-07-14

申请号：US10988658

申请日：2004-11-16

申请人： Koichi Kinoshita ,  Takeshi Ishigaki ,  Yukihiro Urakawa

发明人： Koichi Kinoshita ,  Takeshi Ishigaki ,  Yukihiro Urakawa

IPC分类号： G06F17/50 ,  H01L21/82

CPC分类号： G06F17/5045

摘要： A method for designing a semiconductor integrated circuit, includes placing first, second and third cells, respectively including first stage synchronous circuit having signal propagation time, second stage synchronous circuit having a signal propagation time almost equal to the first stage synchronous circuit, and logic circuit; routing wirings so as to electrically connect the first to third cells; verifying signal propagation timing of the semiconductor integrated circuit having the first to third cells; adjusting the signal propagation timing based on critical path of the signal propagation timing of the semiconductor integrated circuit; and extracting the critical path to replace the second stage synchronous circuit by synchronous circuit of different synchronous type from the first stage synchronous circuit so as to provide a shorter signal propagation time than the first stage synchronous circuit.

摘要翻译： 一种用于设计半导体集成电路的方法，包括分别包括具有信号传播时间的第一级同步电路的第一，第二和第三单元，具有几乎等于第一级同步电路的信号传播时间的第二级同步电路和逻辑电路 ; 路由布线以便电连接第一至第三单元; 验证具有第一至第三小区的半导体集成电路的信号传播定时; 基于半导体集成电路的信号传播定时的关键路径调整信号传播定时; 并通过与第一级同步电路不同同步型的同步电路提取替代第二级同步电路的关键路径，以提供比第一级同步电路更短的信号传播时间。

公开(公告)号：US20060166434A1

公开(公告)日：2006-07-27

申请号：US11320643

申请日：2005-12-30

申请人： Koichi Kinoshita ,  Yukihiro Urakawa

发明人： Koichi Kinoshita ,  Yukihiro Urakawa

IPC分类号： H01L21/8242 ,  H01L23/48 ,  H01L23/52

CPC分类号： G06F17/5068 ,  H01L23/522 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A computer implemented method for designing a semiconductor integrated circuit includes placing dummy pattern on a second interconnection layer positioned just above the first power line based on a placement result of the first power line, the dummy pattern having a long axis parallel with a direction of the first power line; and electrically connecting the dummy pattern to the first power line, based on placement results of the first power line and the dummy pattern.

摘要翻译： 一种用于设计半导体集成电路的计算机实现方法包括：基于第一电力线的放置结果，将伪图案放置在位于第一电力线正上方的第二互连层上，虚设图案具有与第一电力线的方向平行的长轴 第一电力线; 并且基于第一电力线和虚拟图案的配置结果，将虚设图案电连接到第一电力线。

公开(公告)号：US08338964B2

公开(公告)日：2012-12-25

申请号：US13419100

申请日：2012-03-13

申请人： Yukihiro Urakawa

发明人： Yukihiro Urakawa

IPC分类号： H01L23/522

CPC分类号： H01L25/0657 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L28/10 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked-chip device includes a first inductive chip having a first function, a second inductive chip having a second function different from the first function, which is stacked on the first inductive chip, and a third inductive chip having the second function, which is stacked on the second inductive chip. Each of the first, second and third inductive chips has transmitting inductors which transmit data and receiving inductors which receive data. The transmitting inductors and the receiving inductors are disposed in line symmetry to an axis of symmetry. The axes of symmetry of the first, second and third inductive chips are overlapped. Each of the second and third inductive chips is disposed in upside-down or back to front to the first inductive chip.

公开(公告)号：US08000923B2

公开(公告)日：2011-08-16

申请号：US12043584

申请日：2008-03-06

申请人： Takashi Inukai ,  Yukihiro Urakawa

发明人： Takashi Inukai ,  Yukihiro Urakawa

IPC分类号： G01K15/00

CPC分类号： G01K15/002 ,  G01K7/425

摘要： A semiconductor integrated circuit according to the examples of the present invention is applied to a system using a first power source voltage and a second power source voltage independent of the first power source voltage and includes a first area to which the first power source voltage is supplied, a thermal sensor placed in the first area, and a first input path placed in the first area, for transferring trimming data that determine the control contents of the thermal sensor to the thermal sensor.

摘要翻译： 根据本发明的实施例的半导体集成电路被应用于使用与第一电源电压无关的第一电源电压和第二电源电压的系统，并且包括提供第一电源电压的第一区域 放置在第一区域中的热传感器和放置在第一区域中的第一输入路径，用于将确定热传感器的控制内容的修整数据传送到热传感器。

公开(公告)号：US07525132B2

公开(公告)日：2009-04-28

申请号：US11670568

申请日：2007-02-02

申请人： Shinji Kitabayashi ,  Yukihiro Urakawa

发明人： Shinji Kitabayashi ,  Yukihiro Urakawa

IPC分类号： H01L27/10

CPC分类号： G06F17/5077 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： The facility of operation in a manufacturing process and the reliability of the finished product can be improved by making a design based on two basic wiring pattern layers in which wiring traces are formed with regularity, and a basic via array layer inserted between the two basic wiring pattern layers, in which vias are formed with regularity.

摘要翻译： 可以通过基于布置有规则性的两个基本布线图案层进行设计来改进制造工艺中的操作设备和成品的可靠性，以及插入在两个基本布线之间的基本通孔阵列层 图案层，其中通孔形成规则性。

公开(公告)号：US20060224351A1

公开(公告)日：2006-10-05

申请号：US11261536

申请日：2005-10-31

申请人： Takashi Inukai ,  Yukihiro Urakawa

发明人： Takashi Inukai ,  Yukihiro Urakawa

IPC分类号： G01K1/08

CPC分类号： G01K15/002 ,  G01K7/425

摘要： A semiconductor integrated circuit according to the examples of the present invention is applied to a system using a first power source voltage and a second power source voltage independent of the first power source voltage and includes a first area to which the first power source voltage is supplied, a thermal sensor placed in the first area, and a first input path placed in the first area, for transferring trimming data that determine the control contents of the thermal sensor to the thermal sensor.

摘要翻译： 根据本发明的实施例的半导体集成电路被应用于使用与第一电源电压无关的第一电源电压和第二电源电压的系统，并且包括提供第一电源电压的第一区域 放置在第一区域中的热传感器和放置在第一区域中的第一输入路径，用于将确定热传感器的控制内容的修整数据传送到热传感器。

公开(公告)号：US20050134300A1

公开(公告)日：2005-06-23

申请号：US11001155

申请日：2004-12-02

申请人： Natsuki Kushiyama ,  Yukihiro Urakawa

发明人： Natsuki Kushiyama ,  Yukihiro Urakawa

IPC分类号： G01R31/28 ,  G01R31/02 ,  G01R31/30 ,  G01R31/317 ,  H01L21/822 ,  H01L27/04

CPC分类号： G01R31/31725 ,  G01R31/3016

摘要： A semiconductor integrated circuit includes a first delay circuit generating a first delay clock; a second delay circuit generating a second delay clock; a first register registering a value of a first delay of the first delay clock; a second register registering a value of a second delay of the second delay clock; a clock supplying circuit supplying a clock signal to the first and second delay circuits; a phase comparator detecting a phase difference between the first and second delay clocks; and a built-in test circuit configured to control the first and second registers so that the value of the first delay can be registered in the first register and the value of the second delay can be registered in the second register.

摘要翻译： 半导体集成电路包括产生第一延迟时钟的第一延迟电路; 产生第二延迟时钟的第二延迟电路; 注册第一延迟时钟的第一延迟值的第一寄存器; 第二寄存器，其记录所述第二延迟时钟的第二延迟值; 时钟供给电路，向第一和第二延迟电路提供时钟信号; 相位比较器，检测第一和第二延迟时钟之间的相位差; 以及内置测试电路，被配置为控制第一和第二寄存器，使得可以将第一延迟的值登记在第一寄存器中，并且可以将第二延迟的值登记在第二寄存器中。

公开(公告)号：US5517454A

公开(公告)日：1996-05-14

申请号：US355762

申请日：1994-12-14

申请人： Katsuhiko Sato ,  Kiyofumi Ochii ,  Yukihiro Urakawa

发明人： Katsuhiko Sato ,  Kiyofumi Ochii ,  Yukihiro Urakawa

IPC分类号： G11C11/405 ,  G11C11/403 ,  G11C11/406 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A semiconductor memory device including dynamic memory cells for which refresh operation is required, wherein one fundamental cycle consists of a normal operation for carrying out writing or reading into or from the memory cells and a refresh operation. This semiconductor memory device comprising: a refresh signal generating circuit supplied with a clock signal to generate a refresh signal indicating start of refresh; a count signal generating circuit supplied with the clock signal to generate a count signal required for selection of a memory cell to be refreshed, a refresh counter circuit supplied with the refresh signal and the count signal to select a word line and a bit line to which a memory cell to be refreshed is connected; and a precharge circuit supplied with the refresh signal to carry out precharge of the bit line for refresh.

摘要翻译： 一种包括需要刷新操作的动态存储器单元的半导体存储器件，其中一个基本周期包括用于执行对存储器单元的写入或读取的正常操作和刷新操作。 该半导体存储器件包括：刷新信号发生电路，被提供有时钟信号以产生指示刷新开始的刷新信号; 提供有时钟信号的计数信号发生电路，以产生选择要刷新的存储单元所需的计数信号，提供有刷新信号的刷新计数器电路和计数信号以选择字线和位线 连接要更新的存储单元; 以及提供有刷新信号的预充电电路，以执行用于刷新的位线的预充电。