公开(公告)号：US5267177A

公开(公告)日：1993-11-30

申请号：US686461

申请日：1991-04-17

申请人： Koichi Sato ,  Masahiko Toyonaga ,  Toshiro Akino

发明人： Koichi Sato ,  Masahiko Toyonaga ,  Toshiro Akino

IPC分类号： G06F17/50 ,  G06F15/60

CPC分类号： G06F17/5081

摘要： A method for layout compaction which comprises steps of establishing storage areas in a direct access memory as a boundary information memory to which geometrical information on boundaries of a layout is written, searching layout elements of groups adjoining the boundaries of the layout and performing a processing of packing layout elements in a bottom boundary region of the layout and of packing layout elements in a top boundary region of the layout by using the boundary information memory. Thereby, a compaction of the layout can be performed at a high speed.

摘要翻译： 一种用于布局压缩的方法，包括以下步骤：在直接访问存储器中建立存储区域作为写入布局边界的几何信息的边界信息存储器，搜索邻近布局边界的组的布局元素，并执行 通过使用边界信息存储器将布局的底部边界区域中的布局元素和布局的顶部边界区域中的打印布局元素打包。 由此，可以高速地执行布局的压缩。

公开(公告)号：US5159682A

公开(公告)日：1992-10-27

申请号：US426957

申请日：1989-10-26

申请人： Masahiko Toyonaga ,  Toshiro Akino ,  Hiroaki Okude

发明人： Masahiko Toyonaga ,  Toshiro Akino ,  Hiroaki Okude

IPC分类号： G06F17/50 ,  G06Q10/00

CPC分类号： G06Q10/047 ,  G06F17/5072

摘要： During an optimization of an organization of mutually-related elements, an element organization is gradually changed toward an objective specification by local changes of the element organization. A value of an objective function depends on a degree of a nearness of the element organization to the objective specification. A redundancy function of a number of elements in an improvement group is determined in consideration of a fluctuation in the value of the objective function, so that suitable changes of the improvement group are performed by use of the definite redundancy. An intermediate element organization is rejected and accepted in accordance with the redundancy function value, so that a final element organization can be obtained in consideration of a global aspect of the element organization.

公开(公告)号：US06263475B1

公开(公告)日：2001-07-17

申请号：US09192231

申请日：1998-11-16

申请人： Masahiko Toyonaga ,  Toshiro Akino

发明人： Masahiko Toyonaga ,  Toshiro Akino

IPC分类号： G06F1300

CPC分类号： G06F17/5072

摘要： An initial placement is performed based on a net list and a cell library. An optimum effective temperature Tc is derived based on a cost value obtained if the positions of two components, selected from a list of exchange candidates (where all the components are registered), are exchanged with each other and a cost value before the exchange is performed. A first component and a second component, adjacent to the first component, are selected from the list of exchange candidates and the positions thereof are exchanged with each other. And at the optimum effective temperature Tc, it is determined in accordance with a Monte-Carlo method using the cost values before and after the exchange whether or not the exchange is allowable. If it is allowable, the placement after the exchange is decided as a new placement. Otherwise, the placement before the exchange is decided as a new placement. Subsequently, new placements are decided N times for each component included in the list of exchange candidates, and candidate components, the exchange number M of which is equal to or larger than a predetermined number Nm (where Nm

摘要翻译： 基于网络列表和单元库执行初始放置。 如果从交换候选列表中选择的两个组件的位置（其中所有组件被注册）彼此交换并且执行交换之前的成本值，则基于获得的成本值导出最佳有效温度Tc 。 与第一分量相邻的第一分量和第二分量从交换候选列表中选出，其位置彼此交换。 并且在最佳有效温度Tc下，根据蒙特卡罗方法，使用在交换之前和之后的成本值来确定交换是否允许。 如果允许，交换之后的位置被确定为新的位置。 否则，交易所之前的展示位置将被确定为新的展示位置。 随后，为包括在交换候选列表中的每个组件确定新的布局，并且注册其数量M等于或大于预定数量Nm（其中Nm

公开(公告)号：US5490083A

公开(公告)日：1996-02-06

申请号：US130385

申请日：1993-10-01

申请人： Masahiko Toyonaga ,  Michiaki Muraoka ,  Toshiro Akino

发明人： Masahiko Toyonaga ,  Michiaki Muraoka ,  Toshiro Akino

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5045

摘要： The logic elements and net list contained in a logic circuit are inputted to an electronic calculator. The total number N1 of primary adjacent logic circuits which are connected directly to all the logic elements contained in the foregoing logic circuit, respectively is calculated from the inputted logic elements and net list. The total number N2 of primary and secondary adjacent logic circuits, which is the sum of the foregoing total number N1 of primary adjacent logic circuits and the total number of secondary adjacent logic circuits which are connected directly to the primary adjacent logic circuits, respectively, is calculated from the inputted logic elements and net list. The difference between the logarithmic value of the foregoing total number N1 of primary adjacent logic circuits and the logarithmic value of the foregoing total number N2 of primary and secondary adjacent logic circuits is calculated as a value for classification which characterizes the aforesaid logic circuit.

摘要翻译： 包含在逻辑电路中的逻辑元件和网络列表被输入到电子计算器。 从输入的逻辑元件和网络列表中分别计算直接连接到上述逻辑电路中包含的所有逻辑元件的主相邻逻辑电路的总数N1。 主相邻逻辑电路的总数N2是主相邻逻辑电路的前述总数N1和直接连接到主相邻逻辑电路的次相邻逻辑电路的总数之和，分别为 从输入的逻辑元素和网络列表中计算。 主相邻逻辑电路的前述总数N1的对数值与初级和次级相邻逻辑电路的前述总数N2的对数值之间的差被计算为表征上述逻辑电路的分类值。

公开(公告)号：US5852562A

公开(公告)日：1998-12-22

申请号：US571130

申请日：1995-12-12

申请人： Noriko Shinomiya ,  Masahiko Toyonaga ,  Masahiro Fukui ,  Toshiro Akino

发明人： Noriko Shinomiya ,  Masahiko Toyonaga ,  Masahiro Fukui ,  Toshiro Akino

IPC分类号： G06F17/50 ,  G06F17/00

CPC分类号： G06F17/5068

摘要： To reduce a circuit block in area, the present invention provides an LSI layout design method having a cell changing processing for reducing a pure wiring zone in area. By an input processing, circuit design information and cell library are entered. Then, a layout of cells arranged in a plurality of cell rows is designed by a cell placing processing. Then, the height of a wiring zone required between cell rows is estimated by a wiring zone height estimating processing. To reduce the area of a pure wiring zone other than the over-the-cell wiring zones, each of placed cells is changed, by a cell changing processing, to a cell having the same specifications and a different shape or a different terminal position. A layout of cell interconnection is designed by a wiring processing. Based on the layout thus obtained by the processings above-mentioned, a mask pattern is prepared and supplied by a mask pattern preparing processing.

摘要翻译： 为了减少区域中的电路块，本发明提供一种LSI布局设计方法，其具有用于减少区域中的纯布线区的单元改变处理。 通过输入处理，输入电路设计信息和单元库。 然后，通过单元放置处理来设计布置在多个单元行中的单元的布局。 然后，通过布线区高度估计处理来估计单元行之间所需的布线区的高度。 为了减小除了单元布线区域之外的纯布线区域的面积，通过小区改变处理将每个放置的小区改变为具有相同规格和不同形状或不同终端位置的小区。 单元互连的布局是通过布线处理设计的。 基于由上述处理获得的布局，通过掩模图案制备处理制备并提供掩模图案。

公开(公告)号：US5479657A

公开(公告)日：1995-12-26

申请号：US76939

申请日：1993-06-16

申请人： Masahiko Toyonaga ,  Toshiro Akino ,  Hiroaki Okude

发明人： Masahiko Toyonaga ,  Toshiro Akino ,  Hiroaki Okude

IPC分类号： G06F7/24 ,  G06F7/00

CPC分类号： G06F7/24 ,  Y10S707/99937

摘要： A method and system for sorting count information in a computer. Frequencies of usage of count information to be sorted are determined, accumulation information are prepared based on the frequency of usage information. Regarding the accumulation information as the post-sort sequence information, the post-sort information is prepared by using the post-sort sequence information and implementation of the post-sort sequence information.The frequency of usage information designates the write position of the post-sort sequence information and sorts the count information in the ascending or descending order.

摘要翻译： 一种用于对计算机中的计数信息进行排序的方法和系统。 确定要排序的计数信息的使用频率，根据使用信息的频率准备累积信息。 关于累积信息作为分类后序列信息，通过使用分类后序列信息和后分类序列信息的实现来准备分类后信息。 使用信息的频率指定后排序顺序信息的写入位置，并且以升序或降序对计数信息进行排序。

公开(公告)号：US5187668A

公开(公告)日：1993-02-16

申请号：US621893

申请日：1990-12-04

申请人： Hiroaki Okude ,  Masahiko Toyonaga ,  Toshiro Akino

发明人： Hiroaki Okude ,  Masahiko Toyonaga ,  Toshiro Akino

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： There is provided a placement optimization system for determining layout in printed circuits and semiconductor substrates, comprising input means for inputting circuit connection information, placement optimization means for deriving wiring density distribution on the basis of the circuit connection information, evaluating the height and/or width of the wiring region statistically estimated from the wiring density distribution, and output means for outputting the resultant placement position information. Further, the placement optimization system may comprise means for collecting placement elements into sets, determining placement of the sets, then developing the sets into elements, and determining optimum placement positions of the elements.

公开(公告)号：US06292926B1

公开(公告)日：2001-09-18

申请号：US09109042

申请日：1998-07-02

申请人： Masahiro Fukui ,  Masakazu Tanaka ,  Toshiro Akino ,  Masaharu Imai ,  Yoshinori Takeuchi

发明人： Masahiro Fukui ,  Masakazu Tanaka ,  Toshiro Akino ,  Masaharu Imai ,  Yoshinori Takeuchi

IPC分类号： G06F1750

CPC分类号： G06F17/5045 ,  G06F7/5312 ,  G06F7/5443 ,  G06F2207/3884

摘要： The invention provides a functional module model for realizing optimal pipelining. The functional module model includes division line data representing division lines corresponding to positions where pipeline registers can be inserted and delay/area data representing the trade-off relationship between the delay and the area of each division area partitioned by the division lines. By using this functional module model, a pipeline register insertion position is selected among the division lines represented by the division line data, and the delay and the area of each division area are set on the basis of the trade-off relationship represented by the delay/area data. Thus, a pipelined circuit with a minimized area can be synthesized.

摘要翻译： 本发明提供了一种实现最佳流水线功能的模块模型。 功能模块模型包括表示对应于可以插入流水线寄存器的位置的分割线的分割线数据，以及表示延迟与由分割线划分的每个分割区域的区域之间的权衡关系的延迟/面积数据。 通过使用该功能模块模型，在由分割线数据表示的分割线之间选择流水线寄存器插入位置，并且基于由延迟表示的权衡关系来设置每个划分区域的延迟和面积 /区域数据。 因此，可以合成具有最小面积的流水线电路。

公开(公告)号：US5694052A

公开(公告)日：1997-12-02

申请号：US601722

申请日：1996-02-15

申请人： Toshitsugu Sawai ,  Toshiro Akino

发明人： Toshitsugu Sawai ,  Toshiro Akino

IPC分类号： G01R31/26 ,  G01R31/28 ,  G06F15/60

CPC分类号： G01R31/2621

摘要： A characteristic of a MOS transistor is represented using an equivalent model. The equivalent model shows a connection configuration made up of an electric current source which supplies an electric current and a resistor element which is connected in parallel with the electric current source. The electric current is given by the equation of i=G.sub.m .multidot.(V.sub.GS -V.sub.T) for V.sub.GS .gtoreq.V.sub.T where G.sub.m is a coefficient, V.sub.GS is a gate-to-source input voltage of said MOS transistor, and V.sub.T is a given threshold voltage. A plurality of operating zones of the MOS transistor are defined according to the drain, source, and gate terminal voltages of the MOS transistor and are assigned respective values of the coefficient G.sub.m and respective values of the resistor element's resistance. By such a representation, the circuit equation of a semiconductor circuit that is analyzed can be represented in the form of a linear time-invariant equation. Semiconductor circuit performance characteristics can be analyzed and evaluated at high accuracy and high speed.

摘要翻译： 使用等效模型来表示MOS晶体管的特性。 等效模型示出了由提供电流的电流源和与电流源并联连接的电阻元件构成的连接配置。 电流由VGS> / = VT的等式为i = Gmx（VGS-VT）给出，其中Gm是系数，VGS是所述MOS晶体管的栅极 - 源极输入电压，VT是给定阈值 电压。 根据MOS晶体管的漏极，源极和栅极端子电压来定义MOS晶体管的多个工作区域，并分配系数Gm和电阻元件电阻的相应值。 通过这样的表示，分析的半导体电路的电路方程可以以线性时不变方程的形式表示。 半导体电路性能特点可以高精度高速度进行分析和评估。

公开(公告)号：US5677249A

公开(公告)日：1997-10-14

申请号：US670927

申请日：1996-06-26

申请人： Masahiro Fukui ,  Mizuki Segawa ,  Toshiro Akino ,  Michikazu Matsumoto

发明人： Masahiro Fukui ,  Mizuki Segawa ,  Toshiro Akino ,  Michikazu Matsumoto

IPC分类号： H01L23/522 ,  H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/118 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L21/28 ,  H01L27/11807

摘要： A gate wire is formed so as to extend from an active area to a separation, and an impurity diffused area is formed on each side of the gate electrode located on the active area. A contact member for connecting the gate wire to a first layer aluminum interconnection formed in an upper layer of the gate wire is in contact with the gate wire at a portion located on the active area. The utilization ratio of the active area is thus improved, and hence, the width of the separation can be minimized. In addition, by eliminating a mask alignment margin from the gate wire and suppressing the width of the gate wire not to exceed the width of the contact member, the occupied area of a semiconductor apparatus can be reduced.

摘要翻译： 栅极线形成为从有源区域延伸到分离，并且在位于有源区域上的栅电极的每一侧上形成杂质扩散区域。 用于将栅极线连接到形成在栅极线的上层中的第一层铝互连的接触构件在位于有源区上的部分处与栅极线接触。 有效面积的利用率因此提高，因此可以使分离宽度最小化。 此外，通过从栅极线去除掩模对准余量并且抑制栅极线的宽度不超过接触构件的宽度，可以减小半导体装置的占用面积。