公开(公告)号：US4641281A

公开(公告)日：1987-02-03

申请号：US638675

申请日：1984-08-08

申请人： Koichiro Mashiko ,  Michihiro Yamada ,  Kazutami Arimoto ,  Hiroshi Miyamoto ,  Toshifumi Kobayashi ,  Yoshikazu Morooka

发明人： Koichiro Mashiko ,  Michihiro Yamada ,  Kazutami Arimoto ,  Hiroshi Miyamoto ,  Toshifumi Kobayashi ,  Yoshikazu Morooka

IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C7/00

CPC分类号： G11C7/106 ,  G11C11/4091 ,  G11C7/062 ,  G11C7/1051 ,  G11C7/1069

摘要： A dynamic random access memory that contains a memory cell array including a plurality of memory cells includes a pre-amplifier intended to amplify data which is read out from a memory cell accessed by an address signal; a main-amplifier intended to amplify the output of the pre-amplifier and output the amplified signal; and a driver circuit intended to output a driving signal for driving the main-amplifier, the driver circuit includes a first and a second transistor, wherein a drain of the first transistor is connected to a node corresponding to an output terminal of the driver circuit, with a source of the first transistor being earthed and with a gate thereof being connected to the drain of the second transistor, and wherein a gate of the second transistor is connected to the node with a source thereof being earthed.

摘要翻译： 包含包括多个存储单元的存储单元阵列的动态随机存取存储器包括用于放大从由地址信号访问的存储单元读出的数据的前置放大器; 用于放大前置放大器的输出并输出放大信号的主放大器; 以及旨在输出用于驱动主放大器的驱动信号的驱动电路，所述驱动电路包括第一和第二晶体管，其中所述第一晶体管的漏极连接到对应于所述驱动器电路的输出端子的节点， 其中第一晶体管的源极接地并且其栅极连接到第二晶体管的漏极，并且其中第二晶体管的栅极连接到节点，其源极接地。

公开(公告)号：US4689770A

公开(公告)日：1987-08-25

申请号：US792071

申请日：1985-10-28

申请人： Hiroshi Miyamoto ,  Koichiro Mashiko ,  Toshifumi Kobayashi ,  Michihiro Yamada

发明人： Hiroshi Miyamoto ,  Koichiro Mashiko ,  Toshifumi Kobayashi ,  Michihiro Yamada

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C11/24

CPC分类号： G11C5/025 ,  G11C11/4097 ,  G11C7/18 ,  H01L2924/0002

摘要： An LSI semiconductor memory device in which errors in reading out memory cells connected to outermost bit lines of a memory cell array of the device are substantially eliminated. In accordance with the invention, this is done by making capacitances associated with the bit lines of respective ones of the memory cell array substantially equal to one another. To accomplish this, the configuration of an inside portion of wiring other than the bit lines of the array is made the same as that of the bit lines, and the distance between the outermost bit line and the other wiring is made equal to the distance between adjacent ones of the bit lines.

摘要翻译： 基本上消除了读出连接到器件的存储单元阵列的最外位线的存储单元的错误的LSI半导体存储器件。 根据本发明，这是通过使与存储单元阵列中相应的位线相关联的电容基本上彼此相等来实现的。 为了实现这一点，使除阵列的位线之外的布线的内部部分的配置与位线的配置相同，并且使最外侧位线和其它布线之间的距离等于 相邻的位线。

公开(公告)号：US5481496A

公开(公告)日：1996-01-02

申请号：US236004

申请日：1994-05-02

申请人： Toshifumi Kobayashi ,  Yoshikazu Morooka ,  Michihiro Yamada ,  Takeshi Hamamoto

发明人： Toshifumi Kobayashi ,  Yoshikazu Morooka ,  Michihiro Yamada ,  Takeshi Hamamoto

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/065 ,  G11C7/1006 ,  G11C7/12

摘要： Sense amplifiers provided for each of the bit line pairs are divided into groups to be independently driven, whereby the influence of sense amplifiers of different groups can be prevented, and therefore the destruction of data of the non-selected memory cells during data transfer can be prevented. In transferring data from the data register to the memory cell array, the sense amplifier is not activated until the stored information of the memory cells selected by the word line is fully read to the corresponding bit lines, whereby the destruction of data stored in the non-selected memory cells can be prevented.

摘要翻译： 为每个位线对提供的感测放大器被分成要被独立驱动的组，由此可以防止不同组的读出放大器的影响，因此数据传送期间未选择的存储器单元的数据的破坏可以是 防止了 在将数据从数据寄存器传送到存储单元阵列时，读出放大器不会被激活，直到由字线选择的存储单元的存储信息被完全读出到相应的位线为止， 可以防止选择的存储单元。

公开(公告)号：US4982370A

公开(公告)日：1991-01-01

申请号：US357621

申请日：1989-05-23

申请人： Noriaki Matsumoto ,  Toshifumi Kobayashi ,  Koichiro Mashiko

发明人： Noriaki Matsumoto ,  Toshifumi Kobayashi ,  Koichiro Mashiko

IPC分类号： G11C11/401 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4097

CPC分类号： G11C11/4097 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4091

摘要： In a dynamic random access semiconductor memory device comprising a sense amplifier and two pairs of bit lines sharing the sense amplifiers, each of the bit lines having a plurality of memory cells connected thereto, when a memory cell connected to one of the bit-line pairs is selected, the memory cells connected to the other bit-line pair are not connected to the sense amplifier, and, during a refresh cycle for rewriting data into a selected memory cell connected to a bit line of one of the bit-line pairs, the bit lines of the other bit-line pair are disconnected from the sense amplifier.

摘要翻译： 在包括读出放大器和共享读出放大器的两对位线的动态随机存取半导体存储器件中，当存储器单元连接到位线对之一时，每个位线具有连接到其上的多个存储器单元 连接到另一位线对的存储单元不连接到读出放大器，并且在用于将数据重写到连接到位线对之一的位线的选定存储单元的刷新周期期间， 另一位线对的位线与读出放大器断开连接。

公开(公告)号：US4962379A

公开(公告)日：1990-10-09

申请号：US286921

申请日：1988-11-18

申请人： Kenichi Yasuda ,  Toshifumi Kobayashi ,  Michihiro Yamada

发明人： Kenichi Yasuda ,  Toshifumi Kobayashi ,  Michihiro Yamada

IPC分类号： G06F15/16 ,  G06F9/48 ,  G06F13/362 ,  G06F13/364 ,  G06F15/177 ,  H03K3/037 ,  H03K17/00

CPC分类号： G06F13/364

摘要： An arbiter circuit is disclosed for processing requests made at least two subsystems in a multiprocessor system for access to a resource shared by the subsystems. The arbiter circuit includes an SR flip-flop composed of a pair of NAND gates. The flip-flop is operative in response to a time-staggered request signals from the subsystems to provide a request acknowledging signal to the shared resource. When two request signals are simultaneously supplied to the arbiter circuit, the outputs from the pair of NAND gates tend to stay at an intermediate level between the normal two distincitive logic levels, failing to produce an acknowledgment signal. However, the intermediate level of the NAND gate outputs is sensed by a NOR gate to a trigger a switching device into conduction, by means of which one of the intermediate NAND gate outputs is positively shifted to either of the active logic levels for the generation of an acknowledgement signal to the shared resources. Thus, one of the two subsystems is allowed access to the shared resource.

摘要翻译： 公开了一种仲裁器电路，用于处理在多处理器系统中至少两个子系统的请求，以访问子系统共享的资源。 仲裁器电路包括由一对NAND门构成的SR触发器。 触发器响应于来自子系统的时间错误的请求信号而工作，以向共享资源提供请求确认信号。 当两个请求信号同时提供给仲裁器电路时，来自该对NAND门的输出趋向于保持在正常的两个不平等逻辑电平之间的中间电平，不能产生确认信号。 然而，NAND门输出的中间电平由或非门触发，触发开关器件进入导通状态，通过其中的一个中间NAND门输出被积极地移动到任何一个有源逻辑电平以产生 向共享资源发送确认信号。 因此，允许两个子系统之一访问共享资源。

公开(公告)号：US06344622B1

公开(公告)日：2002-02-05

申请号：US09626908

申请日：2000-07-27

申请人： Shuji Takiguchi ,  Toshifumi Kobayashi ,  Atuyoshi Yamaguchi

发明人： Shuji Takiguchi ,  Toshifumi Kobayashi ,  Atuyoshi Yamaguchi

IPC分类号： H01H900

CPC分类号： H01H13/70 ,  H01H2011/0081 ,  H01H2221/018 ,  H01H2223/002

摘要： A switch device includes a key member (4). The key member (4) has a display switch button (13) including a transparent portion through which image information displayed on a display screen of an image display device is transmitted so as to display the image information on an outer side surface of the key member (4). Further, the key member (4) has a button mounting frame (16) including a switch depressing portion (14) operative to switch a switch (6) when the key depressing portion (14) is depressed, and having a button mounting hole portion to which the display switch button (13) is attached. Furthermore, the key member (4) has a waterproof dust cover (19) of a rubber material, which is molded integrally on the button mounting frame (16) to cover the same, and which includes a support portion (17) held in intimate contact with the display screen, and a contractible skirt portion (18). A plurality of resin filling holes are formed in the button mounting frame. The rubber material, forming the waterproof dust cover (19), is filled in the resin filling holes.

摘要翻译： 开关装置包括键构件（4）。 键构件（4）具有显示开关按钮（13），其包括透明部分，通过该透明部分发送显示在图像显示装置的显示屏幕上的图像信息，以便在键部件的外侧表面上显示图像信息 （4）。 此外，键构件（4）具有按钮安装框架（16），该按钮安装框架（16）包括当按压键按压部（14）时可操作地切换开关（6）的开关按压部（14），并且具有按钮安装孔部 显示开关按钮（13）附接到该显示开关按钮。 此外，键构件（4）具有橡胶材料的防水防尘罩（19），其一体地模制在按钮安装框架（16）上以覆盖其上，并且包括保持在亲密的支撑部分（17） 与显示屏幕接触，以及收缩裙部分（18）。 多个树脂填充孔形成在按钮安装框架中。 形成防水防尘罩（19）的橡胶材料填充在树脂填充孔中。

公开(公告)号：US5146300A

公开(公告)日：1992-09-08

申请号：US830971

申请日：1992-02-10

申请人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Tadato Yamagata ,  Masaaki Mihara

发明人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Tadato Yamagata ,  Masaaki Mihara

IPC分类号： G11C15/04 ,  H01L27/108

CPC分类号： H01L27/108 ,  G11C15/043

摘要： A semiconductor integrated circuit device including a semiconductor substrate having a main surface; a first conductive region formed on the main surface; a second conductive region formed on the main surface, spaced apart from the first conductive region and to be electrically connected to the first conductive region; and a capacitor having a storage node connecting the first and second conductive regions. The storage node serves to connect the first and second conductive regions and simultaneously stores charges. In other aspects of the invention, there are provided a memory cell having a structure described above, and a method of manufacturing the above-described semiconductor integrated circuit device.

摘要翻译： 一种半导体集成电路器件，包括：具有主表面的半导体衬底; 形成在所述主表面上的第一导电区域; 形成在所述主表面上的第二导电区域，与所述第一导电区域间隔开并且电连接到所述第一导电区域; 以及具有连接第一和第二导电区域的存储节点的电容器。 存储节点用于连接第一和第二导电区域并同时存储电荷。 在本发明的其他方面，提供了一种具有上述结构的存储单元，以及制造上述半导体集成电路器件的方法。

公开(公告)号：US06670841B2

公开(公告)日：2003-12-30

申请号：US10267666

申请日：2002-10-10

申请人： Toshifumi Kobayashi

发明人： Toshifumi Kobayashi

IPC分类号： H03L500

CPC分类号： H03K17/102 ,  H03K3/356113

摘要： A level shifting circuit includes discharging means made up of a first high-voltage N-type transistor and a second high-voltage N-type transistor whose gates are biased respectively in a predetermined voltage and whose drains are connected to a first and second nodes respectively; and a first low-voltage N-type transistor and a second low-voltage N-type transistor whose drains are connected to sources of the first and second high-voltage N-type transistors respectively, whose gates are connected to the complementary input signal and whose sources are grounded respectively, and the predetermined voltage is set to an intermediate voltage between a threshold voltage of the first and second high-voltage N-type transistors and a breakdown voltage of the first and second low-voltage N-type transistors.

摘要翻译： 电平移动电路包括由第一高压N型晶体管和第二高压N型晶体管构成的放电装置，其栅极分别以预定电压偏置，其漏极分别连接到第一和第二节点 ; 以及第一低压N型晶体管和第二低压N型晶体管，其漏极分别连接到第一和第二高压N型晶体管的源极，栅极连接到互补输入信号， 其源极分别接地，并且将预定电压设置为第一和第二高压N型晶体管的阈值电压与第一和第二低电压N型晶体管的击穿电压之间的中间电压。

公开(公告)号：US5126968A

公开(公告)日：1992-06-30

申请号：US605707

申请日：1990-10-30

申请人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Tadato Yamagata ,  Masaaki Mihara

发明人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Tadato Yamagata ,  Masaaki Mihara

IPC分类号： G11C15/04

CPC分类号： G11C15/043 ,  G11C15/04

摘要： A semiconductor memory device comprises a plurality or CAM cells. In a refreshing operation, data of "1" is applied to all of bit lines and inversion bit lines. In the CAM cells storing the data "1", writing of the data "1" onto the bit lines and the inversion bit lines is performed. Then, the data of "0" is applied to all of the bit lines and the inversion bit lines. In the CAM cells storing the data "0", writing of the data "0" onto the bit lines and the inversion bit lines is performed. In a partial writing operation, in the CAM cells to which writing is performed, a first control node is activated, thereby making it possible to write the CAM cells. In the rest of the CAM cells, the first control node is inactivated, thereby making it impossible to write the CAM cells.

摘要翻译： 半导体存储器件包括多个或多个单元。 在刷新操作中，将数据“1”应用于所有位线和反转位线。 在存储数据“1”的CAM单元中，执行数据“1”到位线和反转位线的写入。 然后，将数据“0”应用于所有的位线和反转位线。 在存储数据“0”的CAM单元中，执行数据“0”到位线和反转位线的写入。 在部分写入操作中，在执行写入的CAM单元中，第一控制节点被激活，从而使得可以写入CAM单元。 在其余的CAM单元中，第一控制节点被去激活，从而不可能写入CAM单元。

公开(公告)号：US4998027A

公开(公告)日：1991-03-05

申请号：US491014

申请日：1990-03-09

申请人： Masaaki Mihara ,  Toshifumi Kobayashi

发明人： Masaaki Mihara ,  Toshifumi Kobayashi

IPC分类号： G06F13/362 ,  G06F13/364 ,  H03K17/00

CPC分类号： G06F13/364

摘要： Disclosed is an arbiter circuit for arbitrating a contention between two request signals which simultaneously attain the H (logical high) level indicating a "request". In this arbiter circuit, buffer circuits, having different input logic threshold voltages, are connected to the respective outputs of two three-input NAND gates. The respective outputs of these two buffer circuits, as signals indicating "acknowledgement" or "negative acknowledgement" of the request signals, are derived as final outputs of the arbiter circuit. One of the buffer circuits has an input logic threshold voltage lower than a logic threshold voltage of the two NAND gates, while the other buffer circuit has an input logic threshold voltage set higher than the logic threshold voltage of the NAND gates. Therefore, when the NAND gates output a voltage with the logic level neither the H level nor the L (logical low) level, a signal of the logic level H indicating the "negative acknowledgement" and a signal of the logical level L indicating the "acknowledgement" are reliably outputted from the buffer circuit with the lower input logic threshold voltage and from the other buffer circuit with the higher input logic threshold voltage, respectively. That is, even if two requests occur simultaneously, one of the request signals is rapidly acknowledged.

摘要翻译： 公开了一种用于仲裁同时达到表示“请求”的H（逻辑高）电平的两个请求信号之间的争用的仲裁电路。 在该仲裁器电路中，具有不同输入逻辑阈值电压的缓冲电路连接到两个三输入NAND门的相应输出。 这两个缓冲电路的各自的输出，作为指示请求信号的“确认”或“否定确认”的信号被导出为仲裁器电路的最终输出。 其中一个缓冲电路具有低于两个NAND门的逻辑阈值电压的输入逻辑阈值电压，而另一个缓冲电路的输入逻辑阈值电压设置为高于NAND门的逻辑门限电压。 因此，当NAND门不产生具有H电平和L（逻辑低）电平的逻辑电平的电压时，指示“否定确认”的逻辑电平H的信号和表示“ 确认“能够从具有较低输入逻辑阈值电压的缓冲电路和具有较高输入逻辑阈值电压的另一缓冲电路可靠地输出。 也就是说，即使两个请求同时发生，一个请求信号被快速确认。