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公开(公告)号：US4641281A
公开(公告)日：1987-02-03
申请号：US638675
申请日：1984-08-08
申请人： Koichiro Mashiko , Michihiro Yamada , Kazutami Arimoto , Hiroshi Miyamoto , Toshifumi Kobayashi , Yoshikazu Morooka
发明人： Koichiro Mashiko , Michihiro Yamada , Kazutami Arimoto , Hiroshi Miyamoto , Toshifumi Kobayashi , Yoshikazu Morooka
IPC分类号： G11C11/407 , G11C7/06 , G11C7/10 , G11C11/4091 , G11C7/00
CPC分类号： G11C7/106 , G11C11/4091 , G11C7/062 , G11C7/1051 , G11C7/1069
摘要： A dynamic random access memory that contains a memory cell array including a plurality of memory cells includes a pre-amplifier intended to amplify data which is read out from a memory cell accessed by an address signal; a main-amplifier intended to amplify the output of the pre-amplifier and output the amplified signal; and a driver circuit intended to output a driving signal for driving the main-amplifier, the driver circuit includes a first and a second transistor, wherein a drain of the first transistor is connected to a node corresponding to an output terminal of the driver circuit, with a source of the first transistor being earthed and with a gate thereof being connected to the drain of the second transistor, and wherein a gate of the second transistor is connected to the node with a source thereof being earthed.
摘要翻译： 包含包括多个存储单元的存储单元阵列的动态随机存取存储器包括用于放大从由地址信号访问的存储单元读出的数据的前置放大器; 用于放大前置放大器的输出并输出放大信号的主放大器; 以及旨在输出用于驱动主放大器的驱动信号的驱动电路，所述驱动电路包括第一和第二晶体管，其中所述第一晶体管的漏极连接到对应于所述驱动器电路的输出端子的节点， 其中第一晶体管的源极接地并且其栅极连接到第二晶体管的漏极，并且其中第二晶体管的栅极连接到节点，其源极接地。
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公开(公告)号：US4689770A
公开(公告)日：1987-08-25
申请号：US792071
申请日：1985-10-28
IPC分类号： G11C11/401 , G11C5/02 , G11C7/18 , G11C11/4097 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C11/24
CPC分类号： G11C5/025 , G11C11/4097 , G11C7/18 , H01L2924/0002
摘要： An LSI semiconductor memory device in which errors in reading out memory cells connected to outermost bit lines of a memory cell array of the device are substantially eliminated. In accordance with the invention, this is done by making capacitances associated with the bit lines of respective ones of the memory cell array substantially equal to one another. To accomplish this, the configuration of an inside portion of wiring other than the bit lines of the array is made the same as that of the bit lines, and the distance between the outermost bit line and the other wiring is made equal to the distance between adjacent ones of the bit lines.
摘要翻译： 基本上消除了读出连接到器件的存储单元阵列的最外位线的存储单元的错误的LSI半导体存储器件。 根据本发明，这是通过使与存储单元阵列中相应的位线相关联的电容基本上彼此相等来实现的。 为了实现这一点，使除阵列的位线之外的布线的内部部分的配置与位线的配置相同，并且使最外侧位线和其它布线之间的距离等于 相邻的位线。
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公开(公告)号：US5375088A
公开(公告)日：1994-12-20
申请号：US149540
申请日：1993-11-09
IPC分类号： G06F11/267 , G11C7/10 , G11C29/26 , G11C29/38 , G11C7/00
CPC分类号： G11C7/10 , G11C29/26 , G11C29/38 , G11C7/1006 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G06F11/267
摘要： A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected to one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.
摘要翻译： 可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。 数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。 在正常模式下读写时，在测试模式下写入期间开关导通，在测试模式下读取期间不导通。 在正常模式和测试模式下，输入数据被施加到连接到块之一的数据总线上，用于在写入期间同时在块中写入。 在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。 在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。
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4.发明授权CMOS dynamic memory device having multiple flip-flop circuits selectively coupled to form sense amplifiers specific to neighboring data bit lines 失效CMOS动态存储器件具有选择性地耦合以形成专用于相邻数据位线的读出放大器的多个触发器电路
公开(公告)号：US5132930A
公开(公告)日：1992-07-21
申请号：US577062
申请日：1990-09-04
IPC分类号： G11C11/4091 , G11C11/4097
CPC分类号： G11C11/4097 , G11C11/4091
摘要： In a metal-oxide semiconductor (MOS) dynamic formed on a semiconductor substrate, data nodes of a first flip-flop are connected to a first pair of folded bit lines. Its power supply node is connected through a switch to a first power supply (Vss). Data nodes of a second flip-flop are connected to a second pair of folded bit lines. Its power supply node is connected through a switch to the first power supply (Vss). A power supply node of a third flip-flop is connected through a switch to a second power supply (Vcc). Data nodes of the third flip-flop are coupled through a first pair of transfer gates to the first pair of the folded bit lines, and through a second pair of transfer gates to the second pair of the folded bit lines. Coupling the first to the third flip-flops forms a first sense amplifier and coupling the second to the third flip-flops forms a second sense amplifier.
摘要翻译： 在半导体衬底上形成的金属氧化物半导体（MOS）动态中，第一触发器的数据节点连接到第一对折叠位线。 其电源节点通过开关连接到第一电源（Vss）。 第二触发器的数据节点连接到第二对折叠位线。 其电源节点通过开关连接到第一电源（Vss）。 第三触发器的电源节点通过开关连接到第二电源（Vcc）。 第三触发器的数据节点通过第一对传输门耦合到第一对折叠位线，并通过第二对传输门耦合到第二对折叠位线。 耦合第一至第三触发器形成第一读出放大器并且将第二触发器耦合到第三触发器形成第二读出放大器。
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公开(公告)号：US4788457A
公开(公告)日：1988-11-29
申请号：US94641
申请日：1987-09-09
IPC分类号： G11C11/408 , G11C8/10 , H03K17/693 , H03M7/00 , H03K19/096
CPC分类号： H03K17/693 , G11C8/10
摘要： A CMOS row decoder circuit in which a row decoder for selecting a single word line from a memory cell array and a column decoder for selecting a single bit line can use in common an internal address signal transmission line. The row decoder circuit comprises a series of MOSFETs of a first conductivity type which is turned on or off in response to address signals selected from external address signals, a second MOSFET of a second conductivity type provided between a power supply potential and the series of MOSFETs and having a gate receiving a first timing signal for providing decoding timing of the address signals, a third MOSFET of the first conductivity type provided between the series of MOSFETs and the second MOSFET and having a gate receiving a first operation timing signal, a fourth MOSFET which is turned on or off in response to a second operation timing signal for transmitting the potential of a node of the second MOSFET and the third MOSFET, and a fifth MOSFET having a gate receiving an output of the fourth MOSFET for transmitting a word line driving signal to a corresponding word line.
摘要翻译： 其中用于从存储单元阵列中选择单个字线的行解码器和用于选择单个位线的列解码器的CMOS行解码器电路可以共同地使用内部地址信号传输线。 行解码器电路包括响应于从外部地址信号中选择的地址信号而导通或截止的第一导电类型的一系列MOSFET，提供在电源电位和一系列MOSFET之间的第二导电类型的第二MOSFET 并且具有接收用于提供所述地址信号的解码定时的第一定时信号的栅极，设置在所述一系列MOSFET和所述第二MOSFET之间并具有接收第一操作定时信号的栅极的第一导电类型的第三MOSFET，第四MOSFET 其响应于用于传输第二MOSFET和第三MOSFET的节点的电位的第二操作定时信号而被接通或关断;以及第五MOSFET，其具有接收用于传输字线驱动的第四MOSFET的输出的栅极 信号到相应的字线。
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6.发明授权
公开(公告)号：US4873669A
公开(公告)日：1989-10-10
申请号：US77306
申请日：1987-07-24
IPC分类号： G11C11/401 , G06F11/267 , G11C7/10 , G11C11/409 , G11C29/00 , G11C29/26 , G11C29/34 , G11C29/38
CPC分类号： G11C7/1057 , G11C29/26 , G11C29/38 , G11C7/10 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1084 , G06F11/267
摘要： A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switches are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected to one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.
摘要翻译： 可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。 数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。 读取和写入时，开关在正常模式下和写入期间在测试模式下导通，并且在测试模式下读取期间不导通。 在正常模式和测试模式下，输入数据被施加到连接到块之一的数据总线上，用于在写入期间同时在块中写入。 在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。 在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。
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7.发明授权Semiconductor memory device having improved interconnection structure of memory cell array 失效具有改善的存储单元阵列的互连结构的半导体存储器件
公开(公告)号：US4833518A
公开(公告)日：1989-05-23
申请号：US094646
申请日：1987-09-09
IPC分类号： H01L27/10 , H01L21/8242 , H01L23/528 , H01L27/108 , H01L29/94
CPC分类号： H01L29/945 , H01L23/528 , H01L27/10805 , H01L27/10829 , H01L2924/0002 , Y10S257/922 , Y10S257/929
摘要： A memory cell array is divided into two groups, one bit line of a pair of bit lines is connected to corresponding memory cells in the first group of the memory cell array, and the other bit line thereof is connected to corresponding memory cells in the second group of the memory cell array.
摘要翻译： 存储单元阵列被分成两组，一对位线的一个位线连接到存储单元阵列的第一组中的相应存储单元，而另一位与第二组中的相应存储单元连接 组的存储单元阵列。
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8.发明授权Dynamic type semiconductor memory device having an error checking and correcting circuit 失效具有错误检查和校正电路的动态型半导体存储器件
公开(公告)号：US5012472A
公开(公告)日：1991-04-30
申请号：US288218
申请日：1988-12-22
IPC分类号： G11C11/413 , G06F11/10 , G11C11/401 , G11C29/00 , G11C29/42 , H01L21/66 , H01L27/10
CPC分类号： G06F11/1008 , G06F11/1076
摘要： In a memory cell comprising a data cell array and a parity cell array, an error checking.multidot.correcting circuit is connected to each of the arrays through a selector. The selector is constituted by transistors connected to each of the bit lines in the memory cell. The number of circuit elements constituting the error checking.multidot.correcting circuit corresponds to one-half of the number of the bit line pairs included in the data cell array and the parity cell array. In an error correcting mode, half of the data appeared on the bit line pairs in data cell array and the parity cell array are transferred to the error checking.multidot.correcting circuit by the selector, so that the errors are corrected. Thereafter, the data of the remaining half of the bit line pairs are processed in the same manner. Therefore, the number of circuit elements of the error checking.multidot.correcting circuit can be reduced compared with the prior art, improving the degree of integration of the device.
摘要翻译： 在包括数据单元阵列和奇偶校验单元阵列的存储单元中，错误校正校正电路通过选择器连接到每个阵列。 选择器由连接到存储单元中每个位线的晶体管构成。 构成误差校正电路的电路元件的数量对应于包括在数据单元阵列和奇偶校验单元阵列中的位线对的数目的一半。 在纠错模式中，一半的数据出现在数据单元阵列中的位线对上，并且奇偶校验单元阵列被选择器传送到错误校正电路，从而纠正错误。 此后，以相同的方式处理剩余的一半的位线对的数据。 因此，与现有技术相比，可以减少误差校正电路的电路元件的数量，从而提高器件的集成度。
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9.发明授权Semiconductor memory device having error correcting circuit and method for correcting error 失效具有误差校正电路的半导体存储器件和用于校正误差的方法
公开(公告)号：US5003542A
公开(公告)日：1991-03-26
申请号：US271491
申请日：1988-11-15
IPC分类号： G11C11/413 , G06F11/10 , G11C11/401 , G11C29/00 , G11C29/42
CPC分类号： G06F11/1008 , G06F11/1076
摘要： In a semiconductor memory device having an error correcting circuit, a pair of bit lines and inverted bit lines are connected to the inputs of first and second inverting amplitude circuits through a first and second N channel MOS transistors, respectively, and the output of the first inverting amplitude circuit is connected to the bit line through a third transistor and the output of the second inverting amplitude circuit is connected to the inverted bit line through a fourth transistor. When an error of information of any bit line pair is detected by an error detecting circuit, the first and second N channel MOS transistors are turned off and each bit line pair is separated from the input of the first and second inverting amplitude circuits and, as a result, information of a bit line pair is rewritten by the output of the first and second inverting amplitude circuits.
摘要翻译： 在具有误差校正电路的半导体存储器件中，一对位线和反相位线分别通过第一和第二N沟道MOS晶体管连接到第一和第二反相幅度电路的输入端，并且第一 反相振幅电路通过第三晶体管连接到位线，并且第二反相幅度电路的输出通过第四晶体管连接到反相位线。 当由错误检测电路检测到任何位线对的信息错误时，第一和第二N沟道MOS晶体管被截止，并且每个位线对与第一和第二反相振幅电路的输入分离，并且如 结果，由第一和第二反相振幅电路的输出重写位线对的信息。
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公开(公告)号：US4817056A
公开(公告)日：1989-03-28
申请号：US077622
申请日：1987-07-24
IPC分类号： G11C11/401 , G11C11/408 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/84
摘要： In a semiconductor memory device of a redundancy configuration having lines (rows or columns) of main memory cells and a line of spare memory cells made to substitute a defective line responsive to the address of the defective line, a comparator compares an address input to the memory device, with the address of the defective line which has been programmed in it, and a spare line selector selects the spare line when the input address is found to coincide with the programmed address. The comparator comprises a dynamic NOR gate having discharge paths each formed of a gate element receiving a bit or its inversion of the input address to be opened or closed depending on the value of the particular bit of the input address currently applied, and a PROM element in series with the gate element. The dynamic NOR gate has a first node forming an output thereof and a second node, each of the series connections of the PROM element and the gate element is connected across the first and the second nodes. The potential on the second node is caused to be identical with the potential on the first node during the precharge period.
摘要翻译： 在具有主存储单元的行（行或列）和响应于缺陷行的地址而替代缺陷行的备用存储单元的行的冗余配置的半导体存储器件中，比较器将输入到 存储器件，其中已经编程的缺陷线的地址，并且当发现输入地址与编程地址一致时，备用线选择器选择备用线。 该比较器包括一个动态或非门，每个放电路径均由栅极元件形成，栅极元件根据当前施加的输入地址的特定位的值接收要打开或关闭的输入地址的位或其反相，以及PROM元件 与门元件串联。 动态NOR门具有形成其输出的第一节点和第二节点，PROM元件和门元件的每个串联连接跨越第一节点和第二节点连接。 在预充电期间，使第二节点上的电位与第一节点上的电位相同。
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