公开(公告)号：US20110248268A1

公开(公告)日：2011-10-13

申请号：US13167762

申请日：2011-06-24

申请人： Koji DAIRIKI ,  Takayuki IKEDA ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Daisuke KAWAE ,  Takayuki INOUE ,  Satoshi KOBAYASHI

发明人： Koji DAIRIKI ,  Takayuki IKEDA ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Daisuke KAWAE ,  Takayuki INOUE ,  Satoshi KOBAYASHI

IPC分类号： H01L29/786

CPC分类号： H01L29/78618 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.

摘要翻译： 为了改善薄膜晶体管的导通电流和截止电流的问题，薄膜晶体管包括一对杂质半导体层，赋予一种导电类型的杂质元素，在其间具有间隔; 在所述栅极绝缘层上与所述栅电极和添加了赋予一种导电类型的杂质元素的所述一对杂质半导体层中的一个重叠的导电层; 以及非晶半导体层，其被连续地设置在赋予一种导电类型的杂质元素的一对杂质半导体层之间，使得非晶半导体层从导电层延伸到栅极绝缘层上并且接触 同时添加赋予一种导电类型的杂质元素的一对杂质半导体层。

公开(公告)号：US20090218568A1

公开(公告)日：2009-09-03

申请号：US12391398

申请日：2009-02-24

申请人： Koji DAIRIKI ,  Takayuki IKEDA ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Daisuke KAWAE ,  Takayuki INOUE ,  Satoshi KOBAYASHI

发明人： Koji DAIRIKI ,  Takayuki IKEDA ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Daisuke KAWAE ,  Takayuki INOUE ,  Satoshi KOBAYASHI

IPC分类号： H01L29/786 ,  H01L33/00

CPC分类号： H01L29/78618 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.

摘要翻译： 为了改善薄膜晶体管的导通电流和截止电流的问题，薄膜晶体管包括一对杂质半导体层，赋予一种导电类型的杂质元素，在其间具有间隔; 在所述栅极绝缘层上与所述栅电极和添加了赋予一种导电类型的杂质元素的所述一对杂质半导体层中的一个重叠的导电层; 以及非晶半导体层，其被连续地设置在赋予一种导电类型的杂质元素的一对杂质半导体层之间，使得非晶半导体层从导电层延伸到栅极绝缘层上并且接触 同时添加赋予一种导电类型的杂质元素的一对杂质半导体层。

公开(公告)号：US20090218572A1

公开(公告)日：2009-09-03

申请号：US12390954

申请日：2009-02-23

申请人： Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Shunpei YAMAZAKI ,  Hiromichi GODO ,  Daisuke KAWAE ,  Satoshi KOBAYASHI

发明人： Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Shunpei YAMAZAKI ,  Hiromichi GODO ,  Daisuke KAWAE ,  Satoshi KOBAYASHI

IPC分类号： H01L33/00 ,  H01L29/786

CPC分类号： H01L29/78609 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/78669

摘要： A thin-film transistor in which problems with ON-state current and OFF-state current are solved, and a thin-film transistor capable of high-speed operation. The thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions, provided with a space therebetween so as to be overlapped with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of semiconductor layers in which an impurity element which serves as an acceptor is added, overlapped over the gate insulating layers with the gate electrode and the impurity semiconductor layers, and disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer being in contact with the gate insulating layer and the pair of semiconductor layers and extended between the pair of semiconductor layers.

摘要翻译： 解决了导通状态电流和截止电流的问题的薄膜晶体管，以及能够进行高速运转的薄膜晶体管。 薄膜晶体管包括一对杂质半导体层，其中添加赋予一种导电类型的杂质元素以形成源极和漏极区域，其间具有间隔，以便与具有栅极绝缘层的栅电极重叠 插入在栅电极和杂质半导体层之间; 添加作为受体的杂质元素的一对半导体层，与栅极电极和杂质半导体层重叠在栅极绝缘层上，并且在沟道长度方向上间隔设置; 以及与所述栅绝缘层和所述一对半导体层接触并在所述一对半导体层之间延伸的非晶半导体层。

公开(公告)号：US20090218576A1

公开(公告)日：2009-09-03

申请号：US12390144

申请日：2009-02-20

申请人： Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Shunpei YAMAZAKI ,  Hiromichi GODO ,  Daisuke KAWAE ,  Satoshi KOBAYASHI

发明人： Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Shunpei YAMAZAKI ,  Hiromichi GODO ,  Daisuke KAWAE ,  Satoshi KOBAYASHI

IPC分类号： H01L33/00 ,  H01L29/786

CPC分类号： H01L27/1214 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765

摘要： A thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions so as to be overlapped at least partly with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of conductive layers which is overlapped over the gate insulating layers at least partly with the gate electrode and the impurity semiconductor layers, and is disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer which is in contact with the gate insulating layer and the pair of conductive layers and is extended between the pair of conductive layers.

摘要翻译： 薄膜晶体管包括一对杂质半导体层，其中添加赋予一种导电类型的杂质元素以形成源极区和漏极区，以至少部分地与栅电极重叠，栅极绝缘层介于 栅电极和杂质半导体层; 一对导电层，其至少部分地与所述栅极电极和所述杂质半导体层重叠在所述栅极绝缘层上方，并且在沟道长度方向上间隔开; 以及与所述栅极绝缘层和所述一对导电层接触并在所述一对导电层之间延伸的非晶半导体层。

公开(公告)号：US20100148175A1

公开(公告)日：2010-06-17

申请号：US12633067

申请日：2009-12-08

申请人： Hiromichi GODO ,  Satoshi KOBAYASHI ,  Hidekazu MIYAIRI ,  Toshiyuki ISA ,  Shunpei YAMAZAKI

发明人： Hiromichi GODO ,  Satoshi KOBAYASHI ,  Hidekazu MIYAIRI ,  Toshiyuki ISA ,  Shunpei YAMAZAKI

IPC分类号： H01L29/786

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L29/04

摘要： Off current of a bottom gate thin film transistor in which a semiconductor layer is shielded from light by a gate electrode is reduced. A thin film transistor includes a gate electrode layer; a first semiconductor layer; a second semiconductor layer, provided on and in contact with the first semiconductor layer; a gate insulating layer between and in contact with the gate electrode layer and the first semiconductor layer; impurity semiconductor layers in contact with the second semiconductor layer; and source and drain electrode layers partially in contact with the impurity semiconductor layers and the first and second semiconductor layers. The entire surface of the first semiconductor layer on the gate electrode layer side is covered by the gate electrode layer; and a potential barrier at a portion where the first semiconductor layer is in contact with the source or drain electrode layer is 0.5 eV or more.

摘要翻译： 其中半导体层被栅极电极遮挡光的底栅薄膜晶体管的截止电流减小。 薄膜晶体管包括栅电极层; 第一半导体层; 第二半导体层，设置在第一半导体层上并与第一半导体层接触; 在栅极电极层和第一半导体层之间并与之接触的栅极绝缘层; 与第二半导体层接触的杂质半导体层; 以及与杂质半导体层和第一和第二半导体层部分接触的源极和漏极电极层。 栅极电极层侧的第一半导体层的整个表面被栅电极层覆盖; 并且在第一半导体层与源极或漏极电极层接触的部分处的势垒为0.5eV以上。

公开(公告)号：US20110175091A1

公开(公告)日：2011-07-21

申请号：US13075436

申请日：2011-03-30

申请人： Satoshi KOBAYASHI ,  Yoshiyuki KUROKAWA ,  Shunpei YAMAZAKI ,  Daisuke KAWAE

发明人： Satoshi KOBAYASHI ,  Yoshiyuki KUROKAWA ,  Shunpei YAMAZAKI ,  Daisuke KAWAE

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L33/02

CPC分类号： H01L29/41733 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696

摘要： To provide a display device having a thin film transistor with high electric characteristics and excellent reliability and a manufacturing method thereof. A gate electrode, a gate insulating film provided over the gate electrode, a first semiconductor layer provided over the gate insulating film and having a microcrystalline semiconductor, a second semiconductor layer provided over the first semiconductor layer and having an amorphous semiconductor, and a source region and a drain region provided over the second semiconductor layer are provided. The first semiconductor layer has high crystallinity than the second semiconductor layer. The second semiconductor layer includes an impurity region having a conductivity type different from a conductivity type of the source region and the drain region between the source region and the drain region.

摘要翻译： 提供具有高电特性和优异可靠性的薄膜晶体管的显示装置及其制造方法。 栅电极，设置在栅电极上的栅极绝缘膜，设置在栅绝缘膜上并具有微晶半导体的第一半导体层，设置在第一半导体层上并具有非晶半导体的第二半导体层，以及源极区 并且设置在第二半导体层上的漏极区。 第一半导体层具有比第二半导体层高的结晶度。 第二半导体层包括具有不同于源极区域的导电类型和源极区域与漏极区域之间的漏极区域的导电类型的杂质区域。

公开(公告)号：US20110303919A1

公开(公告)日：2011-12-15

申请号：US13215469

申请日：2011-08-23

申请人： Satoshi KOBAYASHI ,  Atsushi MIYAGUCHI ,  Yoshitaka MORIYA ,  Yoshiyuki KUROKAWA ,  Daisuke KAWAE

发明人： Satoshi KOBAYASHI ,  Atsushi MIYAGUCHI ,  Yoshitaka MORIYA ,  Yoshiyuki KUROKAWA ,  Daisuke KAWAE

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66765 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/78696

摘要： To provide a display device including a thin film transistor in which high electric characteristics and reduction in off-current can be achieved. The display device having a thin film transistor includes a substrate, a gate electrode provided over the substrate, a gate insulating film provided over the gate electrode, a microcrystalline semiconductor film provided over the gate electrode with the gate insulating film interposed therebetween, a channel protection layer which is provided over and in contact with the microcrystalline semiconductor film, an amorphous semiconductor film provided over the gate insulating film and on a side surface of the microcrystalline semiconductor film and the channel protection layer, an impurity semiconductor layer provided over the amorphous semiconductor film, and a source electrode and a drain electrode provided over and in contact with the impurity semiconductor layer. The thickness of the amorphous semiconductor film is larger than that of the microcrystalline semiconductor film.

摘要翻译： 提供一种显示装置，其具有可以实现高电特性和减少截止电流的薄膜晶体管。 具有薄膜晶体管的显示装置包括基板，设置在基板上的栅极电极，设置在栅电极上的栅极绝缘膜，设置在栅极上的微晶半导体膜，栅极绝缘膜插入其间，沟道保护 提供在微晶半导体膜上并与微晶半导体膜接触的层;非晶半导体膜，设置在栅极绝缘膜上方，并且在微晶半导体膜和沟道保护层的侧表面上，设置在非晶半导体膜上的杂质半导体层 以及设置在杂质半导体层上方并与其接触的源电极和漏电极。 非晶半导体膜的厚度大于微晶半导体膜的厚度。

公开(公告)号：US20100279475A1

公开(公告)日：2010-11-04

申请号：US12839669

申请日：2010-07-20

申请人： Shunpei YAMAZAKI ,  Yoshiyuki KUROKAWA ,  Yasuhiro JINBO ,  Satoshi KOBAYASHI ,  Daisuke KAWAE

发明人： Shunpei YAMAZAKI ,  Yoshiyuki KUROKAWA ,  Yasuhiro JINBO ,  Satoshi KOBAYASHI ,  Daisuke KAWAE

IPC分类号： H01L21/336

CPC分类号： H01L29/4908 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78696

摘要： A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a buffer layer formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the buffer layer, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes an impurity element which serves as a donor.

摘要翻译： 提出了具有优异电特性的薄膜晶体管，具有薄膜晶体管的显示装置，以及制造薄膜晶体管和显示装置的方法。 薄膜晶体管包括形成在栅电极上的栅极绝缘膜，形成在栅极绝缘膜上的微晶半导体膜，形成在微晶半导体膜上的缓冲层，一对半导体膜，赋予一种导电型的杂质元素 并且形成在缓冲层之上，并且在添加有赋予一种导电类型的杂质元素的一对半导体膜上形成的布线。 栅极绝缘膜或整个栅极绝缘膜的一部分和/或微晶半导体的一部分或整个微晶半导体包括用作供体的杂质元素。

公开(公告)号：US20090090909A1

公开(公告)日：2009-04-09

申请号：US12243085

申请日：2008-10-01

申请人： Shunpei YAMAZAKI ,  Yoshiyuki KUROKAWA ,  Daisuke KAWAE ,  Satoshi KOBAYASHI

发明人： Shunpei YAMAZAKI ,  Yoshiyuki KUROKAWA ,  Daisuke KAWAE ,  Satoshi KOBAYASHI

IPC分类号： H01L29/04 ,  H01L21/336

CPC分类号： H01L29/4908 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78696

摘要： To improve field effect mobility of an inverted-staggered TFT using amorphous silicon. In an inverted-staggered TFT, a thin amorphous semiconductor layer which is made to have n-type conductivity is formed between a gate insulating film and an amorphous semiconductor layer. By depositing an amorphous semiconductor layer after a substrate over which up to a gate insulating film is formed is exposed to an atmosphere which contains a phosphine gas in a small amount, an amorphous semiconductor layer which contains phosphorus is formed during the early stage of deposition of the amorphous semiconductor layer. The thus obtained amorphous semiconductor layer has the concentration peak of phosphorus around the surface of the gate insulating film.

摘要翻译： 为了提高使用非晶硅的反交错TFT的场效应迁移率。 在反交错TFT中，在栅极绝缘膜和非晶半导体层之间形成具有n型导电性的薄的非晶半导体层。 通过在其上形成至多栅极绝缘膜的基板之后沉积非晶半导体层，暴露于含有少量磷化氢气体的气氛中，在沉积的早期阶段形成含有磷的非晶半导体层 非晶半导体层。 由此获得的非晶半导体层具有围绕栅极绝缘膜的表面的磷的浓度峰值。

公开(公告)号：US20090114917A1

公开(公告)日：2009-05-07

申请号：US12263702

申请日：2008-11-03

申请人： Shunpei YAMAZAKI ,  Satoshi KOBAYASHI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO

发明人： Shunpei YAMAZAKI ,  Satoshi KOBAYASHI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO

IPC分类号： H01L29/04

CPC分类号： H01L29/04 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78696

摘要： A thin film transistor includes a gate electrode, a gate insulating layer covering the gate electrode, a microcrystalline semiconductor layer over the gate insulating layer, an amorphous semiconductor layer over the microcrystalline semiconductor layer, source and drain regions over the amorphous semiconductor layer, source and drain electrodes in contact with and over the source and drain regions, and a part of the amorphous semiconductor layer overlapping with the source and drain regions is thicker than a part of the amorphous semiconductor layer overlapping with a channel formation region. The side face of the source and drain regions and the side face of the amorphous semiconductor form a tapered shape together with an outmost surface of the amorphous semiconductor layer. The taper angle of the tapered shape is such an angle that decrease electric field concentration around a junction portion between the source and drain regions and the amorphous semiconductor layer.

摘要翻译： 薄膜晶体管包括栅电极，覆盖栅电极的栅极绝缘层，栅极绝缘层上的微晶半导体层，微晶半导体层上的非晶半导体层，非晶半导体层上的源极和漏极区，源极和 与源极和漏极区域接触和超过的漏极电极，与源极和漏极区域重叠的部分非晶半导体层比与沟道形成区域重叠的非晶半导体层的一部分更厚。 源极和漏极区域的侧面和非晶半导体的侧面与非晶半导体层的最外表面一起形成锥形形状。 锥形形状的锥角是减小源极和漏极区域与非晶半导体层之间的接合部周围的电场浓度的角度。