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    Data output circuit that can drive output data speedily and semiconductor memory device including such a data output circuit
    1.
    发明授权
    Data output circuit that can drive output data speedily and semiconductor memory device including such a data output circuit 失效
    能够快速驱动输出数据的数据输出电路和包括这种数据输出电路的半导体存储器件

    公开(公告)号：US06249462B1

    公开(公告)日：2001-06-19

    申请号：US09557867

    申请日：2000-04-24

    申请人： Koji Tanaka ,  Jun Nakai ,  Yasuhiko Tsukikawa ,  Mikio Asakura

    发明人： Koji Tanaka ,  Jun Nakai ,  Yasuhiko Tsukikawa ,  Mikio Asakura

    IPC分类号： G11C1604

    CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C11/4093

    摘要： An output buffer includes a pull up transistor of N type field effect to charge a data output terminal by an external power supply potential Vdd in a high level data output operation, and a pull down transistor of N type field effect to discharge the data output terminal to a ground potential Vss in a low level data output operation. The substrate potential of the pull up NMOS transistor is set to a potential of a level higher than the normal case in a high level data output operation. As a result, the output buffer can speedily charge the data terminal in a high level data output operation.

    摘要翻译： 输出缓冲器包括N型场效应的上拉晶体管，用于在高电平数据输出操作中由外部电源电位Vdd对数据输出端子充电;以及N型场效应的下拉晶体管，以对数据输出端子 到低电平数据输出操作中的地电位Vss。 在高电平数据输出操作中，上拉NMOS晶体管的衬底电位被设置为高于正常情况的电平。 结果，输出缓冲器可以在高电平数据输出操作中对数据终端进行快速充电。

    Semiconductor memory device capable of switching output data width
    2.
    发明授权
    Semiconductor memory device capable of switching output data width 有权
    能够切换输出数据宽度的半导体存储器件

    公开(公告)号：US06687174B2

    公开(公告)日：2004-02-03

    申请号：US10336803

    申请日：2003-01-06

    申请人： Yukiko Maruyama ,  Yasuhiko Tsukikawa ,  Mikio Asakura ,  Takashi Itou

    发明人： Yukiko Maruyama ,  Yasuhiko Tsukikawa ,  Mikio Asakura ,  Takashi Itou

    IPC分类号： G11C700

    CPC分类号： G11C11/4087 ,  G11C7/1045

    摘要： In response to an output data width switching mode signal, a predecoder zone+selector zone outputs selection signals SEL0 to SEL7 and WORDA to WORDC to a preamplifier+write driver zone. The preamplifier+write driver zone can switch connection between global I/O lines GIO to GIO and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.

    摘要翻译： 响应于输出数据宽度切换模式信号，预解码器区域+选择器区域将选择信号SEL0至SEL7和WORDA输出到WORDC到前置放大器+写入驱动器区域。 前置放大器+写入驱动器区可以切换全局I / O线GIO <0>到GIO <7>之间的连接，并响应于这些选择信号切换数据总线。 通过数据总线上的选择器电路等将读取数据输出到焊盘，由此可以在不进行由模式切换或地址变更引起的延迟时间的临界调整的情况下获得简单的结构。

    Semiconductor memory device with test mode decision circuit
    4.
    发明授权
    Semiconductor memory device with test mode decision circuit 失效
    具有测试模式决定电路的半导体存储器件

    公开(公告)号：US06269038B1

    公开(公告)日：2001-07-31

    申请号：US09556290

    申请日：2000-04-24

    申请人： Takashi Itou ,  Yasuhiko Tsukikawa ,  Kengo Aritomi ,  Mikio Asakura

    发明人： Takashi Itou ,  Yasuhiko Tsukikawa ,  Kengo Aritomi ,  Mikio Asakura

    IPC分类号： G11C700

    CPC分类号： G11C29/46

    摘要： There is provided a test mode decision circuit which in the first WCBR cycle responds to an address key by activating a test mode entry signal and with the test mode entry signal activated in the second WCBR cycle responds to an address key by selectively activating test mode signals. In addition to a test mode signal having been activated, the test mode decision circuit further activates another test mode signal. Thus the DRAM hardly enter a test mode erroneously and is also capable of entering more than one test mode simultaneously.

    摘要翻译： 提供了测试模式判定电路，其在第一WCBR周期中通过激活测试模式输入信号来响应地址键，并且在第二WCBR周期中激活的测试模式输入信号通过选择性地激活测试模式信号来响应地址键 。 测试模式判定电路除了测试模式信号被激活之外，还激活另一个测试模式信号。 因此，DRAM几乎不会错误地进入测试模式，并且还能够同时进入多个测试模式。

    Semiconductor memory device having test mode
    5.
    发明授权
    Semiconductor memory device having test mode 失效
    具有测试模式的半导体存储器件

    公开(公告)号：US06201748B1

    公开(公告)日：2001-03-13

    申请号：US09556658

    申请日：2000-04-24

    申请人： Yayoi Nakamura ,  Koji Tanaka ,  Yasuhiko Tsukikawa

    发明人： Yayoi Nakamura ,  Koji Tanaka ,  Yasuhiko Tsukikawa

    IPC分类号： G11C700

    CPC分类号： G11C7/1057 ,  G11C7/1045 ,  G11C7/1051 ,  G11C29/12 ,  G11C29/46

    摘要： In an output buffer of a DRAM, a level shifter outputs a step-up potential responsively when an internal data signal goes low or a test mode signature goes high. An N-channel MOS transistor is rendered conductive in response to the step-up potential from the level shifter, and sets a data input terminal to a power supply potential. The internal data signal and the test mode signature share the level shifter and the N-channel MOS transistor, and hence the layout area can be small and a high-level test mode signature can be output.

    摘要翻译： 在DRAM的输出缓冲器中，当内部数据信号变低或测试模式签名变高时，电平移位器响应地输出升压电位。 N沟道MOS晶体管响应于电平移位器的升压电位而导通，并将数据输入端设置为电源电位。 内部数据信号和测试模式签名共享电平移位器和N沟道MOS晶体管，因此布局面积可以较小，并且可以输出高级测试模式签名。

    Semiconductor memory device driven with low voltage
    8.
    发明申请
    Semiconductor memory device driven with low voltage 失效
    半导体存储器件采用低电压驱动

    公开(公告)号：US20050088881A1

    公开(公告)日：2005-04-28

    申请号：US10972537

    申请日：2004-10-26

    申请人： Takeo Miki ,  Yasuhiko Tsukikawa ,  Shinji Tanaka

    发明人： Takeo Miki ,  Yasuhiko Tsukikawa ,  Shinji Tanaka

    IPC分类号： H01L21/8242 ,  G11C5/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/409 ,  H01L27/108

    CPC分类号： G11C11/4074 ,  G11C5/14

    摘要： Independent power supply systems are provided for a peripheral circuit other than a column decoder, an array-relevant circuit, and a column decoder respectively, so that a peripheral power supply voltage, an array power supply voltage, and a column decoder power supply voltage generated independently of each other are supplied to the peripheral circuit, the array-relevant circuit, and the column decoder as an operating power supply voltage, respectively. Preferably, the column decoder power supply voltage during normal operation is set as an intermediate voltage between the peripheral power supply voltage and the array power supply voltage. Thus, an array configuration suitable for driving a transistor with a low voltage in order to achieve lower power consumption can be obtained.

    摘要翻译： 分别为列解码器，阵列相关电路和列解码器之外的外围电路提供独立电源系统，从而产生外围电源电压，阵列电源电压和列解码器电源电压 彼此独立地分别作为工作电源电压提供给外围电路，阵列相关电路和列解码器。 优选地，正常操作期间的列解码器电源电压被设置为外围电源电压和阵列电源电压之间的中间电压。 因此，可以获得适于驱动具有低电压的晶体管以实现更低功耗的阵列配置。

    Dynamic semiconductor memory device that can control through current of input buffer circuit for external input/output control signal
    9.
    发明授权
    Dynamic semiconductor memory device that can control through current of input buffer circuit for external input/output control signal 失效
    动态半导体存储器件可以通过输入缓冲电路的电流来控制外部输入/输出控制信号

    公开(公告)号：US5619457A

    公开(公告)日：1997-04-08

    申请号：US589687

    申请日：1996-01-22

    申请人： Goro Hayakawa ,  Yasuhiko Tsukikawa

    发明人： Goro Hayakawa ,  Yasuhiko Tsukikawa

    IPC分类号： G11C11/403 ,  G11C7/22 ,  G11C11/406 ,  G11C11/34

    CPC分类号： G11C7/22 ,  G11C11/406

    摘要： A first logic gate circuit receives an internal row strobe signal, an internal column strobe signal and a self refresh mode for providing an operation state detection signal. The operation state detection signal attains an H level when in a stand-by state and a self refresh state. A second CMOS logic gate circuit is closed when the operation state detection signal attains an H level. Therefore, an external input/output control signal is not transmitted to the internal circuit, and a through current does not flow in the CMOS logic gate independent of the level of the external input/output control signal.

    摘要翻译： 第一逻辑门电路接收内部行选通信号，内部列选通信号和用于提供操作状态检测信号的自刷新模式。 当处于待机状态和自刷新状态时，操作状态检测信号达到H电平。 当操作状态检测信号达到H电平时，第二CMOS逻辑门电路闭合。 因此，外部输入/输出控制信号不会发送到内部电路，并且直流电流不会流入CMOS逻辑门，而与外部输入/输出控制信号的电平无关。

    Semiconductor device and level conversion circuit
    10.
    发明申请
    Semiconductor device and level conversion circuit 失效
    半导体器件和电平转换电路

    公开(公告)号：US20070103197A1

    公开(公告)日：2007-05-10

    申请号：US11642726

    申请日：2006-12-21

    申请人： Kyoji Yamasaki ,  Yasuhiko Tsukikawa

    发明人： Kyoji Yamasaki ,  Yasuhiko Tsukikawa

    IPC分类号： H03K19/0175

    CPC分类号： H03K3/356113 ,  H03K3/012 ,  H03K17/223

    摘要： A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.

    摘要翻译： 电平转换电路，将从接收第一电源电压的第二内部电路输出的信号转换为具有与第一电源电压不同的电压电平的第二电源电压的电平的信号，以将其输出信号施加到 第一内部电路设置有用于在第一电源电压被切断时切断通过电平转换电路中的通过电流的路径的机构。