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    QUANTUM DOTS HAVING COMPOSITION GRADIENT SHELL STRUCTURE AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    QUANTUM DOTS HAVING COMPOSITION GRADIENT SHELL STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
    具有组成梯度结构及其制造方法的量子点

    公开(公告)号：US20100140586A1

    公开(公告)日：2010-06-10

    申请号：US12442943

    申请日：2007-09-21

    申请人： Kookheon Char ,  Seonghoon Lee ,  Wan Ki Bae ,  Hyuck Hur

    发明人： Kookheon Char ,  Seonghoon Lee ,  Wan Ki Bae ,  Hyuck Hur

    IPC分类号： H01L29/12 ,  H01L21/36 ,  H01L21/06

    CPC分类号： H01L29/127 ,  B82Y10/00 ,  B82Y30/00 ,  C01B19/002 ,  C01B19/007 ,  C01G9/08 ,  C01G11/00 ,  C01G11/02 ,  C01P2004/03 ,  C01P2004/04 ,  C01P2004/84 ,  C01P2006/40 ,  C09K11/02 ,  C09K11/565 ,  C09K11/883 ,  H01L21/02474 ,  H01L21/02477 ,  H01L21/0248 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02562 ,  H01L21/02601 ,  H01L29/22 ,  Y10S438/962 ,  Y10S977/774

    摘要： Provided are quantum dots having a gradual composition gradient shell structure which have an improvedluminous efficiency and optical stability, and a method of manufacturing the quantum dots in a short amount of time at low cost. In the method, the quantum dots can be manufactured in a short amount of time at low cost using a reactivity difference between semiconductor precursors, unlike in uneconomical and inefficient conventional methods where shells areformed after forming cores and performing cleaning and redispersion processes. Also, formation of the cores is followed by formation of shells having a composition gradient. Thus, even if the shells are formed to a large thickness, the lattice mismatch between cores and shells is relieved. Furthermore, on the basis of the funneling concept, electrons and holes generated in the shells are transferred to the cores to emit light, thereby obtaining a high luminous efficiency of 80% or more. The quantum dot structure is not limited to Group II-IV semiconductor quantum dots but can be applied to other semiconductors quantum dots, such as Group III-V semiconductors quantum dots and Group IV-IV semiconductors quantum dots. Also, the manufacturing method can be utilized in the development of semiconductor quantum dots having different physical properties, and in various other fields.

    摘要翻译： 提供了具有提高的发光效率和光学稳定性的逐渐组成梯度壳结构的量子点以及以低成本在短时间内制造量子点的方法。 在该方法中，可以使用半导体前体之间的反应性差异以低成本在短时间内制造量子点，这不同于在形成核心并执行清洁和再分散工艺之后形成壳体的不经济和低效的常规方法。 此外，芯的形成之后是形成具有组成梯度的壳。 因此，即使壳体形成较大的厚度，也可以减轻芯部和壳体之间的晶格失配。 此外，在漏斗观念的基础上，将壳中产生的电子和空穴转移到核发光，从​​而获得80％以上的高发光效率。 量子点结构不限于II-IV族半导体量子点，而是可以应用于其他半导体量子点，例如III-V族半导体量子点和IV-IV族半导体量子点。 此外，制造方法可以用于开发具有不同物理性质的半导体量子点以及各种其它领域。

    Method and apparatus for high-speed input sampling
    5.
    发明授权
    Method and apparatus for high-speed input sampling 有权
    高速输入采样方法和装置

    公开(公告)号：US07366942B2

    公开(公告)日：2008-04-29

    申请号：US10918008

    申请日：2004-08-12

    申请人： Seonghoon Lee

    发明人： Seonghoon Lee

    IPC分类号： G06F1/04

    CPC分类号： H03K5/135 ,  G11C27/02

    摘要： A signal sampler and method for high-speed input sampling of a signal are disclosed. A first sampler samples a data signal at a rising edge of a clock signal and generates a first sampled signal. A second sampler samples the data signal at a falling edge of an inverted clock signal and generates a second sampled signal. The first and second sampled signals may be combined to determine the next signal sampler output. An evaluation may include asserting the output signal if the first and second sampled signals are asserted, negating the output signal if the first and second sampled signal are negated, and toggling the output signal if the first and second sampled signals are in opposite logic states. The signal sampler and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.

    摘要翻译： 公开了用于信号的高速输入采样的信号采样器和方法。 第一采样器在时钟信号的上升沿采样数据信号并产生第一采样信号。 第二采样器在反相时钟信号的下降沿采样数据信号，并产生第二采样信号。 可以组合第一和第二采样信号以确定下一个信号采样器输出。 如果第一和第二采样信号被断言，评估可以包括断言输出信号，如果第一和第二采样信号被否定则否定输出信号，如果第一和第二采样信号处于相反的逻辑状态，则转换输出信号。 信号采样器和信号采样方法可以结合在半导体器件中，半导体器件可以制造在半导体晶片上并且被包括在电子系统中。

    Multi-phase clock signal generator and method having inherently unlimited frequency capability
    6.
    发明申请
    Multi-phase clock signal generator and method having inherently unlimited frequency capability 有权

    公开(公告)号：US20060203605A1

    公开(公告)日：2006-09-14

    申请号：US11432238

    申请日：2006-05-10

    申请人： Seonghoon Lee

    发明人： Seonghoon Lee

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1072 ,  G11C7/222 ,  H03L7/0805 ,  H03L7/0812

    摘要： A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a variable delay. The first delay line is composed of a plurality of fixed delay units, but no variable delay units. The remaining delay lines are each composed of different numbers of variable delay units to provide respective clock signals having different phases, but they do not include any of the fixed delay units. The first and a last delay line receive an input clock signal. Each of the remaining delay lines are coupled to an output of one of the fixed delay units depending on the number of variable delay units in the delay line so that the resulting clock signals have all been delayed the same number of fixed delay periods.

    Method and apparatus of high-speed input sampling
    7.
    发明申请
    Method and apparatus of high-speed input sampling 有权
    高速输入采样方法和装置

    公开(公告)号：US20070046515A1

    公开(公告)日：2007-03-01

    申请号：US11590582

    申请日：2006-10-31

    申请人： Seonghoon Lee

    发明人： Seonghoon Lee

    IPC分类号： H03M1/00

    CPC分类号： H03K5/135 ,  G11C27/02

    摘要： A signal sampler and method for high-speed input sampling of a signal are disclosed. A first sampler samples a data signal at a rising edge of a clock signal and generates a first sampled signal. A second sampler samples the data signal at a falling edge of an inverted clock signal and generates a second sampled signal. The first and second sampled signals may be combined to determine the next signal sampler output. An evaluation may include asserting the output signal if the first and second sampled signals are asserted, negating the output signal if the first and second sampled signal are negated, and toggling the output signal if the first and second sampled signals are in opposite logic states. The signal sampler and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.

    摘要翻译： 公开了用于信号的高速输入采样的信号采样器和方法。 第一采样器在时钟信号的上升沿采样数据信号并产生第一采样信号。 第二采样器在反相时钟信号的下降沿采样数据信号，并产生第二采样信号。 可以组合第一和第二采样信号以确定下一个信号采样器输出。 如果第一和第二采样信号被断言，评估可以包括断言输出信号，如果第一和第二采样信号被否定则否定输出信号，如果第一和第二采样信号处于相反的逻辑状态，则转换输出信号。 信号采样器和信号采样方法可以结合在半导体器件中，半导体器件可以制造在半导体晶片上并且被包括在电子系统中。

    Method and apparatus for timing domain crossing
    8.
    发明申请
    Method and apparatus for timing domain crossing 失效

    公开(公告)号：US20060044026A1

    公开(公告)日：2006-03-02

    申请号：US10931397

    申请日：2004-08-31

    申请人： Seonghoon Lee ,  J. Johnson

    发明人： Seonghoon Lee ,  J. Johnson

    IPC分类号： H03L7/00

    CPC分类号： G11C11/4076 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4093

    摘要： A timing domain crossing apparatus and method of transferring signals between timing domains are disclosed. A receiver samples a data signal with a sample clock in a first timing domain. The sampled data signal is expanded to a plurality of expansion signals, which are held valid for a plurality of consecutive active clock cycles. A data order adjuster may re-order the plurality of expansion signals to a predetermined order. A timing generator samples a command signal with an internal clock in a second timing domain to generate a re-timing strobe. The re-timing strobe may be temporally positioned to be within the expansion data window and used to sample the plurality of expansion signals in the second timing domain. The timing domain crossing apparatus and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.

    Method and apparatus of high-speed input sampling
    9.
    发明授权
    Method and apparatus of high-speed input sampling 有权
    高速输入采样方法和装置

    公开(公告)号：US07747890B2

    公开(公告)日：2010-06-29

    申请号：US11590582

    申请日：2006-10-31

    申请人： Seonghoon Lee

    发明人： Seonghoon Lee

    IPC分类号： G06F1/04

    CPC分类号： H03K5/135 ,  G11C27/02

    摘要： A signal sampler and method for high-speed input sampling of a signal are disclosed. A first sampler samples a data signal at a rising edge of a clock signal and generates a first sampled signal. A second sampler samples the data signal at a falling edge of an inverted clock signal and generates a second sampled signal. The first and second sampled signals may be combined to determine the next signal sampler output. An evaluation may include asserting the output signal if the first and second sampled signals are asserted, negating the output signal if the first and second sampled signals are negated, and toggling the output signal if the first and second sampled signals are in opposite logic states. The signal sampler and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.

    摘要翻译： 公开了用于信号的高速输入采样的信号采样器和方法。 第一采样器在时钟信号的上升沿采样数据信号并产生第一采样信号。 第二采样器在反相时钟信号的下降沿采样数据信号，并产生第二采样信号。 可以组合第一和第二采样信号以确定下一个信号采样器输出。 如果第一和第二采样信号被断言，评估可以包括断言输出信号，如果第一和第二采样信号被否定则否定输出信号，如果第一和第二采样信号处于相反的逻辑状态，则转换输出信号。 信号采样器和信号采样方法可以结合在半导体器件中，半导体器件可以制造在半导体晶片上并且被包括在电子系统中。

    Method and apparatus for timing domain crossing
    10.
    发明授权
    Method and apparatus for timing domain crossing 有权
    时域交叉的方法和装置

    公开(公告)号：US07375560B2

    公开(公告)日：2008-05-20

    申请号：US11495848

    申请日：2006-07-28

    申请人： Seonghoon Lee ,  J. Brian Johnson

    发明人： Seonghoon Lee ,  J. Brian Johnson

    IPC分类号： H03L7/00

    CPC分类号： G11C11/4076 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4093

    摘要： A timing domain crossing apparatus and method of transferring signals between timing domains are disclosed. A receiver samples a data signal with a sample clock in a first timing domain. The sampled data signal is expanded to a plurality of expansion signals, which are held valid for a plurality of consecutive active clock cycles. A data order adjuster may re-order the plurality of expansion signals to a predetermined order. A timing generator samples a command signal with an internal clock in a second timing domain to generate a re-timing strobe. The re-timing strobe may be temporally positioned to be within the expansion data window and used to sample the plurality of expansion signals in the second timing domain. The timing domain crossing apparatus and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.

    摘要翻译： 公开了一种在定时域之间传送信号的定时域交叉装置和方法。 接收机用第一定时域中的采样时钟对数据信号进行采样。 采样的数据信号被扩展成多个扩展信号，这些扩展信号在多个连续的活动时钟周期中保持有效。 数据顺序调整器可以将多个扩展信号重新排序到预定的顺序。 定时发生器用第二定时域中的内部时钟对命令信号进行采样以产生重新定时选通。 重新定时选通可以在时间上位于扩展数据窗口内，并用于在第二定时域中采样多个扩展信号。 信号采样的定时域交叉装置和方法可以结合在半导体器件中，半导体器件可以制造在半导体晶片上并且被包括在电子系统中。