公开(公告)号：US20100124809A1

公开(公告)日：2010-05-20

申请号：US12271262

申请日：2008-11-14

申请人： Kuang Kian Ong ,  Sai Hooi Yeong ,  Kin Leong Pey ,  Lap Chan ,  Yung Fu Chong

发明人： Kuang Kian Ong ,  Sai Hooi Yeong ,  Kin Leong Pey ,  Lap Chan ,  Yung Fu Chong

IPC分类号： H01L21/336 ,  H01L21/265

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.

摘要翻译： 在结晶半导体衬底中形成浅结区域的方法和具有浅结区域的半导体器件的制造方法包括缺陷工程步骤，其中将第一离子引入到衬底的第一区域中，并且在第一衬底中产生空位 地区。 在产生衬底空位期间，第一区域保持基本上结晶。 在第二区域中产生间质物质，并且将第二离子引入第二区域以捕获间质物质。 激光退火用于激活第一区域中的掺杂物质并修复第二区域中的植入损伤。 缺陷工程过程产生空位丰富的表面区域，其中在MOS器件中产生具有高掺杂剂激活和低薄层电阻的源极和漏极延伸区域。

公开(公告)号：US07888224B2

公开(公告)日：2011-02-15

申请号：US12271262

申请日：2008-11-14

申请人： Kuang Kian Ong ,  Sai Hooi Yeong ,  Kin Leong Pey ,  Lap Chan ,  Yung Fu Chong

发明人： Kuang Kian Ong ,  Sai Hooi Yeong ,  Kin Leong Pey ,  Lap Chan ,  Yung Fu Chong

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.

摘要翻译： 一种在晶体半导体衬底中形成浅结区的方法和用于制造具有浅结区的半导体器件的方法包括：缺陷工程步骤，其中将第一离子引入衬底的第一区域，并且在第一衬底中产生空位 地区。 在产生衬底空位期间，第一区域保持基本上结晶。 在第二区域中产生间质物质，并且将第二离子引入第二区域以捕获间质物质。 激光退火用于激活第一区域中的掺杂物质并修复第二区域中的植入损伤。 缺陷工程过程产生空位丰富的表面区域，其中在MOS器件中产生具有高掺杂剂激活和低薄层电阻的源极和漏极延伸区域。

公开(公告)号：US08338280B2

公开(公告)日：2012-12-25

申请号：US12832082

申请日：2010-07-08

申请人： Dexter Tan ,  Kin Leong Pey ,  Sai Hooi Yeong ,  Yoke King Chin ,  Kuang Kian Ong ,  Chee Mang Ng

发明人： Dexter Tan ,  Kin Leong Pey ,  Sai Hooi Yeong ,  Yoke King Chin ,  Kuang Kian Ong ,  Chee Mang Ng

IPC分类号： H01L21/425

CPC分类号： H01L29/66439 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/7613

摘要： Embodiments relate to a method for fabricating nano-wires in nano-devices, and more particularly to nano-device fabrication using end-of-range (EOR) defects. In one embodiment, a substrate with a surface crystalline layer over the substrate is provided and EOR defects are created in the surface crystalline layer. One or more fins with EOR defects embedded within is formed and oxidized to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wire.

摘要翻译： 实施例涉及一种用于在纳米器件中制造纳米线的方法，更具体地涉及使用端部范围（EOR）缺陷的纳米器件制造。 在一个实施例中，提供了在衬底上具有表面结晶层的衬底，并且在表面晶体层中产生了EOR缺陷。 一个或多个嵌入有EOR缺陷的翅片被形成并被氧化，以在纳米线芯内形成具有纳米晶体的一个或多个完全氧化的纳米线。

公开(公告)号：US08101487B2

公开(公告)日：2012-01-24

申请号：US12466391

申请日：2009-05-15

申请人： Dexter Xueming Tan ,  Benjamin Colombeau ,  Clark Kuang Kian Ong ,  Sai Hooi Yeong ,  Chee Mang Ng ,  Kin Leong Pey

发明人： Dexter Xueming Tan ,  Benjamin Colombeau ,  Clark Kuang Kian Ong ,  Sai Hooi Yeong ,  Chee Mang Ng ,  Kin Leong Pey

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for fabricating a semiconductor device is presented. The method includes providing a substrate and forming a gate stack over the substrate. A first laser processing to form vacancy rich regions within the substrate on opposing sides of the gate stack is performed. The vacancy rich regions have a first depth from a surface of the substrate. A first implant causing end of range defect regions to be formed on opposing sides of the gate stack at a second depth from the surface of the substrate is also carried out, wherein the first depth is proximate to the second depth.

摘要翻译： 提出了一种制造半导体器件的方法。 该方法包括提供衬底并在衬底上形成栅叠层。 执行在栅极堆叠的相对侧上在衬底内形成空位丰富区域的第一激光处理。 空位丰富区域具有从基板表面的第一深度。 还执行第一种植入物，其在基板的表面的第二深度处形成在栅堆叠的相对侧上形成范围缺陷区域的端部，其中第一深度接近第二深度。

公开(公告)号：US08053340B2

公开(公告)日：2011-11-08

申请号：US11862213

申请日：2007-09-27

申请人： Benjamin Colombeau ,  Sai Hooi Yeong ,  Francis Benistant ,  Bangun Indajang ,  Lap Chan

发明人： Benjamin Colombeau ,  Sai Hooi Yeong ,  Francis Benistant ,  Bangun Indajang ,  Lap Chan

IPC分类号： H01L21/425 ,  H01L21/22 ,  H01L21/38

CPC分类号： H01L29/78612 ,  H01L29/66537 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78621

摘要： A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.

摘要翻译： 一种晶体管，其包括设置在与栅极的相对侧相邻的衬底中的晕圈。 晕区具有上部和下部区域。 上部区域是具有多余空位的结晶区域，下部区域是非晶区域。 源极/漏极扩散区域设置在光晕区域中。 源极/漏极扩散区域与上部和下部晕圈重叠。 该架构提供最小的延伸电阻以及最小的横向扩散，以实现更好的CMOS器件缩放。

公开(公告)号：US08354321B2

公开(公告)日：2013-01-15

申请号：US13277197

申请日：2011-10-19

申请人： Benjamin Colombeau ,  Sai Hooi Yeong ,  Francis Benistant ,  Bangun Indajang ,  Lap Chan

发明人： Benjamin Colombeau ,  Sai Hooi Yeong ,  Francis Benistant ,  Bangun Indajang ,  Lap Chan

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L29/78612 ,  H01L29/66537 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78621

摘要： A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.

摘要翻译： 一种晶体管，其包括设置在与栅极的相对侧相邻的衬底中的晕圈。 晕区具有上部和下部区域。 上部区域是具有多余空位的结晶区域，下部区域是非晶区域。 源极/漏极扩散区域设置在光晕区域中。 源极/漏极扩散区域与上部和下部晕圈重叠。 该架构提供最小的延伸电阻以及最小的横向扩散，以实现更好的CMOS器件缩放。

公开(公告)号：US08268733B2

公开(公告)日：2012-09-18

申请号：US12537268

申请日：2009-08-07

申请人： Dexter Tan ,  Chee Chong Lim ,  Sai Hooi Yeong ,  Chee Mang Ng

发明人： Dexter Tan ,  Chee Chong Lim ,  Sai Hooi Yeong ,  Chee Mang Ng

IPC分类号： H01L21/263

CPC分类号： F27B17/0025 ,  H01L21/2686 ,  H01L21/67115

摘要： A method of forming a device is presented. The method includes providing a wafer having an active surface and dividing the wafer into a plurality of portions. The wafer is selectively processed by localized heating of a first of the plurality of portions. The wafer is then repeatedly selectively processed by localized heating of a next of the plurality of portions until all plurality of portions have been selectively processed.

摘要翻译： 提出了一种形成装置的方法。 该方法包括提供具有活性表面并将晶片分成多个部分的晶片。 通过对多个部分中的第一部分的局部加热选择性地处理晶片。 然后通过对多个部分中的下一个的局部加热来重复地选择性地处理晶片，直到所有多个部分已被选择性地处理。

公开(公告)号：US08153537B1

公开(公告)日：2012-04-10

申请号：US13236627

申请日：2011-09-19

申请人： Sai Hooi Yeong ,  Tao Wang ,  Shesh Mani Pandey ,  Chia Ching Yeo ,  Ying Keung Leung ,  Elgin Kiok Boone Quek

发明人： Sai Hooi Yeong ,  Tao Wang ,  Shesh Mani Pandey ,  Chia Ching Yeo ,  Ying Keung Leung ,  Elgin Kiok Boone Quek

IPC分类号： H01L21/469 ,  H01L21/31

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

摘要： There is provided a method for fabricating a semiconductor device comprising the formation of a first device in the first device region, the first device comprising first diffusion regions. A stressor layer covering the substrate in the first device region and the first device is subsequently formed, the stressor layer having a first stress value. A laser anneal to memorize at least a portion of the first stress value in the first device is carried out followed by an activation anneal after the laser anneal to activate dopants in the first diffusion regions.

摘要翻译： 提供了一种用于制造半导体器件的方法，包括在第一器件区域中形成第一器件，第一器件包括第一扩散区域。 随后形成覆盖第一器件区域中的衬底和第一器件的应力层，该应力层具有第一应力值。 进行激光退火以存储第一器件中的第一应力值的至少一部分，随后在激光退火之后激活退火以激活第一扩散区域中的掺杂剂。