公开(公告)号：US06271570B1

公开(公告)日：2001-08-07

申请号：US09578414

申请日：2000-05-26

申请人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

发明人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/76895 ,  H01L29/66545

摘要： A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact. A tungsten layer is selectively deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines to form polycide gate electrodes and interconnection lines. The dielectric material layer is anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

摘要翻译： 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，在那里它们不被掩模覆盖以形成多晶硅栅电极和具有其上的氮化硅层的互连线，其中在栅电极和互连线之间留有间隙。 介电材料层沉积在衬底上以填充间隙。 去除了掩模层。 此后，多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 将离子注入到开口内的半导体衬底中以形成掩埋接触。 选择性地沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的钨层以形成多晶硅栅极电极和互连线。 电介质材料层被各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

公开(公告)号：US6080647A

公开(公告)日：2000-06-27

申请号：US34927

申请日：1998-03-05

申请人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

发明人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/3205

CPC分类号： H01L29/6659 ,  H01L21/76895 ,  H01L29/66545

摘要： A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact. A tungsten layer is selectively deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines to form polycide gate electrodes and interconnection lines. The dielectric material layer is anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

摘要翻译： 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，在那里它们不被掩模覆盖以形成多晶硅栅电极和具有其上的氮化硅层的互连线，其中在栅电极和互连线之间留有间隙。 介电材料层沉积在衬底上以填充间隙。 去除了掩模层。 此后，多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 将离子注入到开口内的半导体衬底中以形成掩埋接触。 选择性地沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的钨层以形成多晶硅栅极电极和互连线。 电介质材料层被各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

公开(公告)号：US5960276A

公开(公告)日：1999-09-28

申请号：US161406

申请日：1998-09-28

申请人： Jhon-Jhy Liaw ,  Dun-Nian Yaung ,  Jin-Yuan Lee

发明人： Jhon-Jhy Liaw ,  Dun-Nian Yaung ,  Jin-Yuan Lee

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L21/76

CPC分类号： H01L21/76229 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/823878

摘要： A method to form, in a NMOS area, a shallow trench isolation (STI) having B doped sidewalls regions 44 to reduce the NMOS reverse narrow width effect in narrow active areas 12N (e.g., narrow channel regions

摘要翻译： 在NMOS区域中形成具有B掺杂侧壁区域44的浅沟槽隔离（STI）以减小窄有源区12N（例如窄通道区域<0.1μm宽）中的NMOS反向窄宽度效应的方法。 提供具有NMOS区域13和PMOS区域15的衬底。衬底氧化物层20和阻挡层22形成在衬底上。 沟槽24在NMOS和PMOS区域中的衬底10中蚀刻。 蚀刻形成窄的有源区域12N和宽的有源区域12W。 狭窄的有源区域12N具有在0.4和1.0μm之间的宽度。 在衬底上的沟槽的侧壁和底部上生长衬里层30。 形成第一光致抗蚀剂层，覆盖PMOS区域并且在NMOS区域上具有第一开口。 在关键步骤中，在衬底中形成硼掺杂区域44的沟槽的侧壁和底部中进行大角度硼注入。 去除第一光致抗蚀剂层。 绝缘层50形成在NMOS和PMOS区域的沟槽中。 PMOS区域中的PMOS场效应晶体管和NMOS区域中的NMOS场效应晶体管形成。 本发明的硼掺杂区域44减小了NMOS区域中的反向窄的宽效应。

公开(公告)号：US06265295B1

公开(公告)日：2001-07-24

申请号：US09389889

申请日：1999-09-03

申请人： Yi-Miaw Lin ,  Jhon-Jhy Liaw ,  Dun-Nian Yaung

发明人： Yi-Miaw Lin ,  Jhon-Jhy Liaw ,  Dun-Nian Yaung

IPC分类号： H01L213205

CPC分类号： H01L21/76832 ,  H01L21/31053 ,  H01L21/3143 ,  H01L21/31612 ,  H01L21/76828 ,  H01L21/76829

摘要： A new method is provided for the creation of metal plugs. After the gate electrode structures have been created on the surface of a semiconductor substrate, the Inter Level Dielectric (ILD) is deposited over the poly gates. The layer of ILD is polished, a second layer of dielectric is deposited over the layer of ILD. A stop layer is deposited over the second layer of dielectric, a Rapid Thermal Annealing (RTA) is performed to the stop layer and the thin layer of dielectric. The metal plugs are then patterned and deposited after which the process proceeds for the further creation of the interconnect metal.

摘要翻译： 提供了一种用于创建金属插头的新方法。 在半导体衬底的表面上形成栅电极结构之后，层间介质（ILD）沉积在多晶硅栅极上。 抛光ILD层，在ILD层上沉积第二层电介质。 在第二层电介质上沉积停止层，对停止层和电介质层进行快速热退火（RTA）。 然后对金属插塞进行图案化和沉积，然后进行该工艺以进一步制造互连金属。

公开(公告)号：US06071798A

公开(公告)日：2000-06-06

申请号：US156361

申请日：1998-09-18

申请人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Jhon-Jhy Liaw

发明人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Jhon-Jhy Liaw

IPC分类号： H01L21/027 ,  H01L21/265 ,  H01L21/768 ,  H01L21/425

CPC分类号： H01L21/0274 ,  H01L21/76895 ,  H01L21/26506

摘要： The present invention provides a novel method for fabricating a buried contact extending under the first conductive layer 16 and subjacent first insulating layer 14. A first insulating layer 14 and a first conductive layer are formed over a silicon substrate 10 having isolation structures 12. A photoresist mask 18A having a buried contact opening 20 is formed over the first conductive layer. The first conductive layer 16 and the first insulating layer 14 are etched through the photoresist mask 18A. A width 21 of the photoresist mask 18A adjacent to the buried contact opening 20 is removed using a descum process, thereby forming an expanded opening 20A and an exposed ring 16A of the first conductive layer 16 with subjacent first insulating layer 14. Impurity ions 23 are implanted through the expanded opening 20A at a sufficient energy level to form a novel buried contact region 22 comprising an extended buried contact region 22A extending under the exposed ring 16A of the first conductive layer 16 and an exposed area 22B where the first conductive layer and the first insulating layer were removed. The photoresist mask 18A is removed. A second conductive layer 24 and a polycide layer 26 are formed over the first conductive layer 16 and over the exposed area 22B of the buried contact region 22. The polycide layer 26, the second conductive layer 24, the first conductive layer 16 and the first insulating layer 14 are patterned to form a second opening 30 partially overlapping the extended buried contact region and defining a gate structure 31 and a contact structure 33. Lightly doped source/drain regions 32, sidewall spacers 34, and source/drain structures 38 are formed.

摘要翻译： 本发明提供一种用于制造在第一导电层16和相​​邻的第一绝缘层14之下延伸的掩埋触点的新方法。在具有隔离结构12的硅衬底10上形成第一绝缘层14和第一导电层。 在第一导电层上形成具有埋入接触开口20的掩模18A。 通过光致抗蚀剂掩模18A蚀刻第一导电层16和第一绝缘层14。 使用除尘工艺去除与掩埋接触开口20相邻的光致抗蚀剂掩模18A的宽度21，从而在第一绝缘层14的下方形成第一导电层16的扩展开口20A和暴露环16A。杂质离子23 通过膨胀的开口20A以足够的能级注入，以形成新颖的埋入接触区域22，其包括在第一导电层16的暴露环16A下面延伸的延伸的掩埋接触区域22A和暴露区域22B，其中第一导电层和 去除第一绝缘层。 去除光致抗蚀剂掩模18A。 在第一导电层16上方和掩埋接触区域22的暴露区域22B之上形成第二导电层24和多晶硅化物层26.多晶硅化物层26，第二导电层24，第一导电层16和第一导电层16 图案化绝缘层14以形成与扩展掩埋接触区域部分重叠并限定栅极结构31和接触结构33的第二开口30。形成轻掺杂的源极/漏极区域32，侧壁间隔物34以及源极/漏极结构38 。

公开(公告)号：US09368388B2

公开(公告)日：2016-06-14

申请号：US13446199

申请日：2012-04-13

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L27/11 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

CPC分类号： H01L27/0924 ,  H01L21/76232 ,  H01L21/823431 ,  H01L27/1104 ,  H01L29/66818 ,  H01L29/7853

摘要： A FinFET comprises an isolation region formed in a substrate, a reverse T-shaped fin formed in the substrate, wherein a bottom portion of the reverse T-shaped fin is enclosed by the isolation region and an upper portion of the reverse T-shaped fin protrudes above a top surface of the isolation region. The FinFET further comprises a gate electrode wrapping the reverse T-shaped fin.

公开(公告)号：US08750011B2

公开(公告)日：2014-06-10

申请号：US13423968

申请日：2012-03-19

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： G11C5/06

CPC分类号： G11C17/12 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11226 ,  H01L27/1211

摘要： A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a first second-level contact formed on the first first-level contact, wherein the first second-level contact shifts in a first direction with reference to the first first-level contact. The ROM cell further comprises a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is aligned with the first first-level contact and a second second-level formed on the second first-level contact, wherein the second second-level contact shifts in a second direction with reference to the second first-level contact, and wherein the first direction is opposite to the second direction.

摘要翻译： ROM单元包括形成在存储单元的晶体管的第一有源区上的第一第一电平触点，形成在第一第一级触点上的第一二级触点，其中第一二级触点以第一 方向参考第一级联系人。 ROM单元还包括形成在存储器单元的晶体管的第二有源区上的第二第一电平触点，其中第二第一电平触点与第一第一电平触点对准，第二二级触点形成在第二电平触点上 第二第一级触点，其中所述第二二级触头相对于所述第二第一级触点沿第二方向移动，并且其中所述第一方向与所述第二方向相反。

公开(公告)号：US08625334B2

公开(公告)日：2014-01-07

申请号：US13328685

申请日：2011-12-16

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  H01L27/1104

摘要： A memory cell and array and a method of forming a memory cell and array are described. A memory cell includes first and second pull-up transistors, first and second pull-down transistors, first and second pass-gate transistors, and first and second isolation transistors. Drains of the first pull-up and first pull-down transistors are electrically coupled together at a first node. Drains of the second pull-up and second pull-down transistors are electrically coupled together at a second node. Gates of the second pull-up and second pull-down transistors are electrically coupled to the first node, and gates of the first pull-up and first pull-down transistors are electrically coupled to the second node. The first and second pass-gate transistors are electrically coupled to the first and second nodes, respectively. The first and second isolation transistors are electrically coupled to the first and second nodes, respectively.

公开(公告)号：US20130270652A1

公开(公告)日：2013-10-17

申请号：US13446199

申请日：2012-04-13

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/088

CPC分类号： H01L27/0924 ,  H01L21/76232 ,  H01L21/823431 ,  H01L27/1104 ,  H01L29/66818 ,  H01L29/7853

摘要： A FinFET comprises an isolation region formed in a substrate, a reverse T-shaped fin formed in the substrate, wherein a bottom portion of the reverse T-shaped fin is enclosed by the isolation region and an upper portion of the reverse T-shaped fin protrudes above a top surface of the isolation region. The FinFET further comprises a gate electrode wrapping the reverse T-shaped fin.

摘要翻译： FinFET包括形成在衬底中的隔离区域，形成在衬底中的反向T形翅片，其中反向T形翅片的底部被隔离区域包围，并且反向T形翅片的上部 突出在隔离区域的顶表面上方。 FinFET还包括一个包围反向T形翅片的栅电极。

公开(公告)号：US08409964B2

公开(公告)日：2013-04-02

申请号：US13399488

申请日：2012-02-17

申请人： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

发明人： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

IPC分类号： H01L21/76

CPC分类号： H01L21/823878 ,  H01L21/76232

摘要： A shallow trench isolation (STI) structure and methods of forming a STI structure are disclosed. An embodiment is a method for forming a semiconductor structure. The method includes forming a recess in a semiconductor substrate; forming a first material on sidewalls of the recess; forming a widened recessed portion through a bottom surface of the recess; removing the first material from the sidewalls of the recess; and forming a dielectric material in the recess and the widened recessed portion. The bottom surface of the recess is exposed through the first material, and the bottom surface of the recess has a first width. The widened recessed portion has a second width. The second width is greater than the first width.

摘要翻译： 公开了浅沟槽隔离（STI）结构和形成STI结构的方法。 实施例是形成半导体结构的方法。 该方法包括在半导体衬底中形成凹陷; 在所述凹部的侧壁上形成第一材料; 通过所述凹部的底面形成加宽的凹部; 从所述凹部的侧壁去除所述第一材料; 以及在所述凹部和所述加宽的凹部中形成介电材料。 凹部的底面通过第一材料露出，凹部的底面具有第一宽度。 加宽的凹部具有第二宽度。 第二宽度大于第一宽度。