公开(公告)号：US06071798A

公开(公告)日：2000-06-06

申请号：US156361

申请日：1998-09-18

申请人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Jhon-Jhy Liaw

发明人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Jhon-Jhy Liaw

IPC分类号： H01L21/027 ,  H01L21/265 ,  H01L21/768 ,  H01L21/425

CPC分类号： H01L21/0274 ,  H01L21/76895 ,  H01L21/26506

摘要： The present invention provides a novel method for fabricating a buried contact extending under the first conductive layer 16 and subjacent first insulating layer 14. A first insulating layer 14 and a first conductive layer are formed over a silicon substrate 10 having isolation structures 12. A photoresist mask 18A having a buried contact opening 20 is formed over the first conductive layer. The first conductive layer 16 and the first insulating layer 14 are etched through the photoresist mask 18A. A width 21 of the photoresist mask 18A adjacent to the buried contact opening 20 is removed using a descum process, thereby forming an expanded opening 20A and an exposed ring 16A of the first conductive layer 16 with subjacent first insulating layer 14. Impurity ions 23 are implanted through the expanded opening 20A at a sufficient energy level to form a novel buried contact region 22 comprising an extended buried contact region 22A extending under the exposed ring 16A of the first conductive layer 16 and an exposed area 22B where the first conductive layer and the first insulating layer were removed. The photoresist mask 18A is removed. A second conductive layer 24 and a polycide layer 26 are formed over the first conductive layer 16 and over the exposed area 22B of the buried contact region 22. The polycide layer 26, the second conductive layer 24, the first conductive layer 16 and the first insulating layer 14 are patterned to form a second opening 30 partially overlapping the extended buried contact region and defining a gate structure 31 and a contact structure 33. Lightly doped source/drain regions 32, sidewall spacers 34, and source/drain structures 38 are formed.

摘要翻译： 本发明提供一种用于制造在第一导电层16和相​​邻的第一绝缘层14之下延伸的掩埋触点的新方法。在具有隔离结构12的硅衬底10上形成第一绝缘层14和第一导电层。 在第一导电层上形成具有埋入接触开口20的掩模18A。 通过光致抗蚀剂掩模18A蚀刻第一导电层16和第一绝缘层14。 使用除尘工艺去除与掩埋接触开口20相邻的光致抗蚀剂掩模18A的宽度21，从而在第一绝缘层14的下方形成第一导电层16的扩展开口20A和暴露环16A。杂质离子23 通过膨胀的开口20A以足够的能级注入，以形成新颖的埋入接触区域22，其包括在第一导电层16的暴露环16A下面延伸的延伸的掩埋接触区域22A和暴露区域22B，其中第一导电层和 去除第一绝缘层。 去除光致抗蚀剂掩模18A。 在第一导电层16上方和掩埋接触区域22的暴露区域22B之上形成第二导电层24和多晶硅化物层26.多晶硅化物层26，第二导电层24，第一导电层16和第一导电层16 图案化绝缘层14以形成与扩展掩埋接触区域部分重叠并限定栅极结构31和接触结构33的第二开口30。形成轻掺杂的源极/漏极区域32，侧壁间隔物34以及源极/漏极结构38 。

公开(公告)号：US5960276A

公开(公告)日：1999-09-28

申请号：US161406

申请日：1998-09-28

申请人： Jhon-Jhy Liaw ,  Dun-Nian Yaung ,  Jin-Yuan Lee

发明人： Jhon-Jhy Liaw ,  Dun-Nian Yaung ,  Jin-Yuan Lee

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L21/76

CPC分类号： H01L21/76229 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/823878

摘要： A method to form, in a NMOS area, a shallow trench isolation (STI) having B doped sidewalls regions 44 to reduce the NMOS reverse narrow width effect in narrow active areas 12N (e.g., narrow channel regions

摘要翻译： 在NMOS区域中形成具有B掺杂侧壁区域44的浅沟槽隔离（STI）以减小窄有源区12N（例如窄通道区域<0.1μm宽）中的NMOS反向窄宽度效应的方法。 提供具有NMOS区域13和PMOS区域15的衬底。衬底氧化物层20和阻挡层22形成在衬底上。 沟槽24在NMOS和PMOS区域中的衬底10中蚀刻。 蚀刻形成窄的有源区域12N和宽的有源区域12W。 狭窄的有源区域12N具有在0.4和1.0μm之间的宽度。 在衬底上的沟槽的侧壁和底部上生长衬里层30。 形成第一光致抗蚀剂层，覆盖PMOS区域并且在NMOS区域上具有第一开口。 在关键步骤中，在衬底中形成硼掺杂区域44的沟槽的侧壁和底部中进行大角度硼注入。 去除第一光致抗蚀剂层。 绝缘层50形成在NMOS和PMOS区域的沟槽中。 PMOS区域中的PMOS场效应晶体管和NMOS区域中的NMOS场效应晶体管形成。 本发明的硼掺杂区域44减小了NMOS区域中的反向窄的宽效应。

公开(公告)号：US06635936B1

公开(公告)日：2003-10-21

申请号：US09616975

申请日：2000-07-14

申请人： Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Dun-Nian Yaung ,  Jeng-Han Lee

发明人： Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Dun-Nian Yaung ,  Jeng-Han Lee

IPC分类号： H01L2976

CPC分类号： H01L27/1112 ,  Y10S257/903

摘要： An SRAM device has STI regions separated by mesas and doped regions including source/drain regions, active areas, wordline conductors and contacts in a semiconductor substrate is made with a source region has 90° transitions in critical locations. Form a dielectric layer above the active areas. Form the wordline conductors above the active areas transverse to the active areas. The source and drain regions of a pass gate transistor are on the opposite sides of a wordline conductor. Form the sidewalls along the crystal plane. Form the contacts extending down through to the dielectric layer to the mesas. Substrate stress is reduced because the large active area region formed in the substrate assures that the contacts are formed on the surfaces of the mesas are in contact with the mesas formed on the substrate and that the surfaces of the silicon of the mesas are shielded from the contacts.

摘要翻译： SRAM器件具有通过台面分隔的STI区域，并且包括源极/漏极区域，有源区域，字线导体和半导体衬底中的触点的掺杂区域由源区域在关键位置具有90°转变而制成。 在有效区域之上形成介电层。 在横向于有效区域的有效区域之上形成字线导体。 栅极晶体管的源极和漏极区域位于字线导体的相对侧。 沿着<100>晶面形成侧壁。 形成触点向下延伸到电介质层到台面。 衬底应力减小，因为形成在衬底中的大的有源区域区域确保在台面的<100>表面上形成的触点与形成在衬底上的台面接触，并且硅的<110>表面 台面与触点屏蔽。

公开(公告)号：US5926697A

公开(公告)日：1999-07-20

申请号：US947793

申请日：1997-10-09

申请人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Hsien Wei Chin

发明人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Hsien Wei Chin

IPC分类号： H01L21/02 ,  H01L21/761 ,  H01L23/525 ,  H01L21/76

CPC分类号： H01L28/87 ,  H01L21/761 ,  H01L23/5258 ,  H01L2924/0002

摘要： An improved and new structure and method for forming a guard ring in an integrated circuit having at least one level of polysilicon wiring has been developed. The guard ring is formed without necessitating additional manufacturing process steps and the guard ring is bonded to the semiconductor substrate, thereby providing a superior barrier to diffusion of moisture and contaminants from a window in the insulating layers to the semiconductor device regions.

摘要翻译： 已经开发了用于在具有至少一个级别的多晶硅布线的集成电路中形成保护环的改进和新的结构和方法。 保护环形成，而不需要额外的制造工艺步骤，并且保护环结合到半导体衬底，从而为水分和污染物从绝缘层中的窗口扩散到半导体器件区域提供了优越的屏障。

公开(公告)号：US6117722A

公开(公告)日：2000-09-12

申请号：US252464

申请日：1999-02-18

申请人： Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Dun-Nian Yaung ,  Jeng-Han Lee

发明人： Shou-Gwo Wuu ,  Jin-Yuan Lee ,  Dun-Nian Yaung ,  Jeng-Han Lee

IPC分类号： H01L27/11 ,  H01L21/8234

CPC分类号： H01L27/1112 ,  Y10S257/903

摘要： An SRAM device has STI regions separated by mesas and doped regions including source/drain regions, active areas, wordline conductors and contacts in a semiconductor substrate is made with a source region has 90.degree. transitions in critical locations. Form a dielectric layer above the active areas. Form the wordline conductors above the active areas transverse to the active areas. The source and drain regions of a pass gate transistor are on the opposite sides of a wordline conductor. Form the sidewalls along the crystal plane. Form the contacts extending down through to the dielectric layer to the mesas. Substrate stress is reduced because the large active area region formed in the substrate assures that the contacts are formed on the surfaces of the mesas are in contact with the mesas formed on the substrate and that the surfaces of the silicon of the mesas are shielded from the contacts.

摘要翻译： SRAM器件具有通过台面分隔的STI区域，并且包括源极/漏极区域，有源区域，字线导体和半导体衬底中的触点的掺杂区域由源区域在关键位置具有90°转变而制成。 在有效区域之上形成介电层。 在横向于有效区域的有效区域之上形成字线导体。 栅极晶体管的源极和漏极区域位于字线导体的相对侧。 沿着<100>晶面形成侧壁。 形成触点向下延伸到电介质层到台面。 衬底应力减小，因为形成在衬底中的大的有源区域区域确保在台面的<100>表面上形成的触点与形成在衬底上的台面接触，并且硅的<110>表面 台面与触点屏蔽。

公开(公告)号：US6136633A

公开(公告)日：2000-10-24

申请号：US222272

申请日：1998-12-28

申请人： Dun-Nian Yaung ,  Jin-Yuan Lee ,  Shou-Gwo Wuu

发明人： Dun-Nian Yaung ,  Jin-Yuan Lee ,  Shou-Gwo Wuu

IPC分类号： H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8244 ,  H01L23/535 ,  H01L27/11 ,  H01L29/78 ,  H01L21/44 ,  H01L21/76 ,  H01L21/8234

CPC分类号： H01L29/6659 ,  H01L21/743 ,  H01L21/76202 ,  H01L23/535 ,  H01L27/11 ,  H01L29/7833 ,  H01L2924/0002

摘要： A new method of forming an improved buried contact junction is described. A gate oxide layer is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited over the gate oxide layer. A photoresist mask is formed over the first polysilicon layer having an opening over the planned buried contact. The first polysilicon layer not covered by the photoresist mask is etched away. A portion of the photoresist mask at the edges of the opening is cut away to expose a portion of the first polysilicon layer at the edges of the opening. The gate oxide layer not covered by the mask is etched away using a reduced etching selectivity of oxide to silicon so that an upper portion of the first polysilicon layer exposed at the edges of the opening is etched away leaving a thinner first polysilicon layer at the edges of the opening. Ions are implanted through the opening and through the thinner first polysilicon layer into the semiconductor substrate to form the buried contact. The photoresist mask is removed and a second polysilicon layer is deposited overlying the first polysilicon layer and the buried contact to complete formation of the buried contact.

摘要翻译： 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅氧化层。 第一多晶硅层沉积在栅极氧化物层上。 在第一多晶硅层上形成光致抗蚀剂掩模，该多晶硅层在预定的埋入触点上具有开口。 未被光致抗蚀剂掩模覆盖的第一多晶硅层被蚀刻掉。 在开口的边缘处的光致抗蚀剂掩模的一部分被切除，以在开口的边缘处露出第一多晶硅层的一部分。 使用氧化物对硅的蚀刻选择性降低，掩模未被掩模覆盖的栅极氧化物层被蚀刻掉，使得在开口边缘暴露的第一多晶硅层的上部被蚀刻掉，在边缘处留下较薄的第一多晶硅层 的开幕。 离子通过开口并通过较薄的第一多晶硅层注入到半导体衬底中以形成埋入触点。 去除光致抗蚀剂掩模，并且沉积覆盖第一多晶硅层和埋入触点的第二多晶硅层以完成掩埋触点的形成。

公开(公告)号：US06271570B1

公开(公告)日：2001-08-07

申请号：US09578414

申请日：2000-05-26

申请人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

发明人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/76895 ,  H01L29/66545

摘要： A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact. A tungsten layer is selectively deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines to form polycide gate electrodes and interconnection lines. The dielectric material layer is anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

摘要翻译： 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，在那里它们不被掩模覆盖以形成多晶硅栅电极和具有其上的氮化硅层的互连线，其中在栅电极和互连线之间留有间隙。 介电材料层沉积在衬底上以填充间隙。 去除了掩模层。 此后，多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 将离子注入到开口内的半导体衬底中以形成掩埋接触。 选择性地沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的钨层以形成多晶硅栅极电极和互连线。 电介质材料层被各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

公开(公告)号：US06265295B1

公开(公告)日：2001-07-24

申请号：US09389889

申请日：1999-09-03

申请人： Yi-Miaw Lin ,  Jhon-Jhy Liaw ,  Dun-Nian Yaung

发明人： Yi-Miaw Lin ,  Jhon-Jhy Liaw ,  Dun-Nian Yaung

IPC分类号： H01L213205

CPC分类号： H01L21/76832 ,  H01L21/31053 ,  H01L21/3143 ,  H01L21/31612 ,  H01L21/76828 ,  H01L21/76829

摘要： A new method is provided for the creation of metal plugs. After the gate electrode structures have been created on the surface of a semiconductor substrate, the Inter Level Dielectric (ILD) is deposited over the poly gates. The layer of ILD is polished, a second layer of dielectric is deposited over the layer of ILD. A stop layer is deposited over the second layer of dielectric, a Rapid Thermal Annealing (RTA) is performed to the stop layer and the thin layer of dielectric. The metal plugs are then patterned and deposited after which the process proceeds for the further creation of the interconnect metal.

摘要翻译： 提供了一种用于创建金属插头的新方法。 在半导体衬底的表面上形成栅电极结构之后，层间介质（ILD）沉积在多晶硅栅极上。 抛光ILD层，在ILD层上沉积第二层电介质。 在第二层电介质上沉积停止层，对停止层和电介质层进行快速热退火（RTA）。 然后对金属插塞进行图案化和沉积，然后进行该工艺以进一步制造互连金属。

公开(公告)号：US6080647A

公开(公告)日：2000-06-27

申请号：US34927

申请日：1998-03-05

申请人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

发明人： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/3205

CPC分类号： H01L29/6659 ,  H01L21/76895 ,  H01L29/66545

摘要： A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact. A tungsten layer is selectively deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines to form polycide gate electrodes and interconnection lines. The dielectric material layer is anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

摘要翻译： 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，在那里它们不被掩模覆盖以形成多晶硅栅电极和具有其上的氮化硅层的互连线，其中在栅电极和互连线之间留有间隙。 介电材料层沉积在衬底上以填充间隙。 去除了掩模层。 此后，多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 将离子注入到开口内的半导体衬底中以形成掩埋接触。 选择性地沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的钨层以形成多晶硅栅极电极和互连线。 电介质材料层被各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

公开(公告)号：US07935994B2

公开(公告)日：2011-05-03

申请号：US11066432

申请日：2005-02-24

申请人： Wen-De Wang ,  Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Chung-Yi Yu

发明人： Wen-De Wang ,  Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Chung-Yi Yu

IPC分类号： H01L31/062

CPC分类号： H01L27/14654 ,  H01L27/14623 ,  H01L27/14636 ,  H01L2924/0002 ,  H01L2924/00

摘要： System and method for providing a light shield for a CMOS imager is provided. The light shield comprises a structure formed above a point between a photo-sensitive element and adjacent circuitry. The structure is formed of a light-blocking material, such as a metal, metal alloy, metal compound, or the like, formed in dielectric layers over the photo-sensitive elements.

摘要翻译： 提供了一种用于为CMOS成像器提供遮光罩的系统和方法。 光屏蔽包括形成在感光元件和相邻电路之间的点之上的结构。 该结构由光敏元件上的电介质层中形成的诸如金属，金属合金，金属化合物等的遮光材料形成。