公开(公告)号：US20110074030A1

公开(公告)日：2011-03-31

申请号：US12570941

申请日：2009-09-30

申请人： Kuo Liang Wei ,  Hsu Sheng Yu ,  Hong-Ji Lee

发明人： Kuo Liang Wei ,  Hsu Sheng Yu ,  Hong-Ji Lee

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/53223 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76852 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines

摘要翻译： 半导体器件及其制造方法包括提供包括绝缘基底层和下部和上部阻挡层之间的导电层的堆叠结构，蚀刻层叠结构以提供多个导电柱，每个导电柱从下部延伸 阻挡层，每个导电柱具有由蚀刻的上阻挡层形成的覆盖的上阻挡层帽，其中下阻挡层被部分地蚀刻以在每个导电线之间提供焊盘区域，在蚀刻 层叠结构，暴露所述焊盘区域，以及蚀刻所述衬垫层并去除所述暴露的焊盘区域以形成多条导电线

公开(公告)号：US08076778B2

公开(公告)日：2011-12-13

申请号：US12570941

申请日：2009-09-30

申请人： Kuo Liang Wei ,  Hsu Sheng Yu ,  Hong-Ji Lee

发明人： Kuo Liang Wei ,  Hsu Sheng Yu ,  Hong-Ji Lee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/40

CPC分类号： H01L23/53223 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76852 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines.

摘要翻译： 半导体器件及其制造方法包括提供包括绝缘基底层和下部和上部阻挡层之间的导电层的堆叠结构，蚀刻层叠结构以提供多个导电柱，每个导电柱从下部延伸 阻挡层，每个导电柱具有由蚀刻的上阻挡层形成的覆盖的上阻挡层帽，其中下阻挡层被部分地蚀刻以在每个导电线之间提供焊盘区域，在蚀刻 层叠结构，暴露所述焊盘区域，以及蚀刻所述衬垫层并去除所述暴露的焊盘区域以形成多条导电线。

公开(公告)号：US08372714B2

公开(公告)日：2013-02-12

申请号：US12824757

申请日：2010-06-28

申请人： Kuo Liang Wei ,  Hong-Ji Lee

发明人： Kuo Liang Wei ,  Hong-Ji Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28114 ,  H01L21/02071 ,  H01L21/28123 ,  H01L21/32137 ,  H01L21/32139

摘要： A semiconductor device can be manufactured by a method that includes forming a structure that includes a plurality of layers of semiconductor material. One or more etching processes are performed on the multi-layered semiconductor structure, and then an Ar/O2 treatment is performed on the multi-layered semiconductor structure. The Ar/O2 treatment includes exposure of the structure to Ar ion bombardment and O2 molecular oxidation. The Ar/O2 treatment can be used to create a bottle-shaped structure.

摘要翻译： 可以通过包括形成包括多层半导体材料的结构的方法来制造半导体器件。 对多层半导体结构进行一个以上的蚀刻处理，然后对多层半导体结构进行Ar / O 2处理。 Ar / O2处理包括将结构暴露于Ar离子轰击和O2分子氧化。 Ar / O2处理可用于制造瓶形结构。

公开(公告)号：US20110316096A1

公开(公告)日：2011-12-29

申请号：US12824757

申请日：2010-06-28

申请人： Kuo Liang Wei ,  Hong-Ji Lee

发明人： Kuo Liang Wei ,  Hong-Ji Lee

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L21/28

CPC分类号： H01L21/28114 ,  H01L21/02071 ,  H01L21/28123 ,  H01L21/32137 ,  H01L21/32139

摘要： A semiconductor device can be manufactured by a method that includes forming a structure that includes a plurality of layers of semiconductor material. One or more etching processes are performed on the multi-layered semiconductor structure, and then an Ar/O2 treatment is performed on the multi-layered semiconductor structure. The Ar/O2 treatment includes exposure of the structure to Ar ion bombardment and O2 molecular oxidation. The Ar/O2 treatment can be used to create a bottle-shaped structure.

摘要翻译： 可以通过包括形成包括多层半导体材料的结构的方法来制造半导体器件。 对多层半导体结构进行一个以上的蚀刻处理，然后对多层半导体结构进行Ar / O 2处理。 Ar / O2处理包括将结构暴露于Ar离子轰击和O2分子氧化。 Ar / O2处理可用于制造瓶形结构。

公开(公告)号：US07410593B2

公开(公告)日：2008-08-12

申请号：US11359787

申请日：2006-02-22

申请人： Hong-Ji Lee ,  Shih-Ping Hong ,  An-Chyi Wei

发明人： Hong-Ji Lee ,  Shih-Ping Hong ,  An-Chyi Wei

IPC分类号： B44C1/22 ,  H01L21/302

CPC分类号： H01L21/3065

摘要： Methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas and one or more process gases into the chamber; and etching the substrate, wherein the introduction of the N2 gas is stopped prior to etching, and wherein etching comprises an initial plasma ignition wherein at least a portion of the N2 gas remains present in the chamber during initial plasma ignition. Additional methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas and one or more process gases into the chamber; applying power to an electrode in the chamber such that an N2 memory species is formed; and etching the substrate, where the introduction of the N2 gas into the chamber can be stopped prior to etching. Other methods are also described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas into the chamber; applying power to an electrode in the chamber such that an N2 memory species is formed; removing the applied power from the electrode in the chamber; stopping the introduction of the N2 gas into the chamber and introducing one or more process gases into the chamber; and etching the substrate.

摘要翻译： 描述了包括：提供具有蚀刻室的等离子体蚀刻装置的方法; 将待蚀刻的基板设置在所述室中; 将N 2 O 2气体和一种或多种工艺气体引入所述室中; 以及蚀刻所述衬底，其中在蚀刻之前停止引入N 2 O 2气体，并且其中蚀刻包括初始等离子体点火，其中N 2 N 2 N 2的至少一部分 初始等离子体点火期间气体保留在腔室中。 描述了附加方法，其包括：提供具有蚀刻室的等离子体蚀刻装置; 将待蚀刻的基板设置在所述室中; 将N 2 O 2气体和一种或多种工艺气体引入所述室中; 向腔室中的电极施加功率，使得形成N 2种记忆物质; 并且在蚀刻之前可以停止引入N 2气体到腔室中的衬底。 还描述了其它方法，其包括：提供具有蚀刻室的等离子体蚀刻装置; 将待蚀刻的基板设置在所述室中; 将N 2 O 2气体引入室中; 向腔室中的电极施加功率，使得形成N 2种记忆物质; 从室中的电极去除施加的功率; 停止将N 2 N 2气体引入室中并将一种或多种工艺气体引入室中; 并蚀刻衬底。

公开(公告)号：US20070193977A1

公开(公告)日：2007-08-23

申请号：US11359787

申请日：2006-02-22

申请人： Hong-Ji Lee ,  Shih-Ping Hong ,  An-Chyi Wei

发明人： Hong-Ji Lee ,  Shih-Ping Hong ,  An-Chyi Wei

IPC分类号： C23F1/00 ,  C03C25/68 ,  H01L21/302

CPC分类号： H01L21/3065

摘要： Methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas and one or more process gases into the chamber; and etching the substrate, wherein the introduction of the N2 gas is stopped prior to etching, and wherein etching comprises an initial plasma ignition wherein at least a portion of the N2 gas remains present in the chamber during initial plasma ignition. Additional methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas and one or more process gases into the chamber; applying power to an electrode in the chamber such that an N2 memory species is formed; and etching the substrate, where the introduction of the N2 gas into the chamber can be stopped prior to etching. Other methods are also described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas into the chamber; applying power to an electrode in the chamber such that an N2 memory species is formed; removing the applied power from the electrode in the chamber; stopping the introduction of the N2 gas into the chamber and introducing one or more process gases into the chamber; and etching the substrate.

摘要翻译： 描述了包括：提供具有蚀刻室的等离子体蚀刻装置的方法; 将待蚀刻的基板设置在所述室中; 将N 2 O 2气体和一种或多种工艺气体引入所述室中; 以及蚀刻所述衬底，其中在蚀刻之前停止引入N 2 O 2气体，并且其中蚀刻包括初始等离子体点火，其中N 2 N 2 N 2的至少一部分 初始等离子体点火期间气体保留在腔室中。 描述了附加方法，其包括：提供具有蚀刻室的等离子体蚀刻装置; 将待蚀刻的基板设置在所述室中; 将N 2 O 2气体和一种或多种工艺气体引入所述室中; 向腔室中的电极施加功率，使得形成N 2种记忆物质; 并且在蚀刻之前可以停止引入N 2气体到腔室中的衬底。 还描述了其它方法，其包括：提供具有蚀刻室的等离子体蚀刻装置; 将待蚀刻的基板设置在所述室中; 将N 2 N 2气体引入所述室中; 向腔室中的电极施加功率，使得形成N 2种记忆物质; 从室中的电极去除施加的功率; 停止将N 2 N 2气体引入室中并将一种或多种工艺气体引入室中; 并蚀刻衬底。

公开(公告)号：US20110104881A1

公开(公告)日：2011-05-05

申请号：US12611614

申请日：2009-11-03

申请人： Hong-Ji Lee ,  Nan-Tsu Lian ,  Kuang-Chao Chen

发明人： Hong-Ji Lee ,  Nan-Tsu Lian ,  Kuang-Chao Chen

IPC分类号： H01L21/28

CPC分类号： H01L21/28247 ,  H01L21/28282 ,  H01L27/11568

摘要： A method of fabricating a memory device includes providing a substrate having an insulating layer, forming first, second, and third conductive layers on the insulating layer, forming a mask on the third conductive layer, etching through the third conductive layer and a first portion thickness of the second conductive layer using the mask to provide an etched sidewall portions of the third conductive layer and an etched upper surface of the second polysilicon layer, and forming a liner layer along the etched sidewall portions and the etched upper surface.

摘要翻译： 一种制造存储器件的方法包括提供具有绝缘层的衬底，在绝缘层上形成第一，第二和第三导电层，在第三导电层上形成掩模，蚀刻通过第三导电层和第一部分厚度 使用所述掩模提供所述第三导电层的蚀刻侧壁部分和所述第二多晶硅层的蚀刻的上表面，以及沿着蚀刻的侧壁部分和所蚀刻的上表面形成衬垫层。

公开(公告)号：US20100167021A1

公开(公告)日：2010-07-01

申请号：US12345305

申请日：2008-12-29

申请人： Hong-Ji Lee ,  Shih-Ping Hong ,  Fang-Hao Hsu

发明人： Hong-Ji Lee ,  Shih-Ping Hong ,  Fang-Hao Hsu

IPC分类号： B32B3/10 ,  G03F7/20

CPC分类号： H01L21/31116 ,  H01L21/0332 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139

摘要： A method of forming a semiconductor structure is provided. First, a target layer and a mask layer are sequentially formed on a substrate. Thereafter, a first pattern transfer layer having a plurality of openings is formed on the mask layer. Afterwards, a second pattern transfer layer is formed in the openings of the first pattern transfer layer. The mask layer is then patterned, using the first pattern transfer layer and the second pattern transfer layer as a mask, so as to form a patterned mask layer. Further, the target layer is patterned using the patterned mask layer.

摘要翻译： 提供一种形成半导体结构的方法。 首先，在基板上依次形成目标层和掩模层。 此后，在掩模层上形成具有多个开口的第一图案转印层。 之后，在第一图案转印层的开口中形成第二图案转印层。 然后使用第一图案转印层和第二图案转印层作为掩模将掩模层图案化，以形成图案化掩模层。 此外，使用图案化掩模层对目标层进行图案化。

公开(公告)号：US06319858B1

公开(公告)日：2001-11-20

申请号：US09613318

申请日：2000-07-11

申请人： Hong-Ji Lee ,  David Guang-Kai Jeng

发明人： Hong-Ji Lee ,  David Guang-Kai Jeng

IPC分类号： H01L2131

CPC分类号： H01L21/02131 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/31695

摘要： Disclosed is a non-solvent method for reducing a dielectric constant of a dielectric film. The dielectric film, which can be formed on a substrate by a spin-on coating or a chemical vapor deposition (CVD), is placed in an atmosphere of an inert gas at a high pressure or in a supercritical fluid state, and then the pressure of the atmosphere is rapidly released to form nanopores on the surface of the dielectric film, whereby the dielectric constant thereof is reduced.

摘要翻译： 公开了用于降低电介质膜的介电常数的非溶剂方法。 可以通过旋涂或化学气相沉积（CVD）在基板上形成的电介质膜置于高压或超临界流体状态的惰性气体气氛中，然后将压力 的气氛被快速释放以在电介质膜的表面上形成纳米孔，由此其介电常数降低。

公开(公告)号：US5698644A

公开(公告)日：1997-12-16

申请号：US789654

申请日：1997-01-27

申请人： Andrew Teh Hu ,  Hong-Ji Lee ,  Tein-Sone Chen

发明人： Andrew Teh Hu ,  Hong-Ji Lee ,  Tein-Sone Chen

IPC分类号： C08F2/34 ,  C08F4/64 ,  C08F4/642 ,  C08F12/04

CPC分类号： C08F12/04 ,  C08F4/65912 ,  Y02P20/544

摘要： Syndiotactic polymers of vinyl aromatic monomers are synthesized in the presence of a catalytic system consisting of a commercial titanium compound and methylaluminoxane under high pressure and/or supercritical state of inert gas such as argon or nitrogen.

摘要翻译： 乙烯基芳族单体的间同立构聚合物是在惰性气体例如氩气或氮气的高压和/或超临界状态下，在由市售的钛化合物和甲基铝氧烷组成的催化体系的存在下合成的。