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    Voltage characteristic regulating method of latch circuit, voltage characteristic regulating method of semiconductor device, and voltage characteristic regulator of latch circuit
    1.
    发明授权
    Voltage characteristic regulating method of latch circuit, voltage characteristic regulating method of semiconductor device, and voltage characteristic regulator of latch circuit 失效
    锁存电路的电压特性调节方法，半导体器件的电压特性调节方法和锁存电路的电压特性调节器

    公开(公告)号：US08618870B2

    公开(公告)日：2013-12-31

    申请号：US13377009

    申请日：2010-06-11

    申请人： Toshiro Hiramoto ,  Takayasu Sakurai ,  Makoto Suzuki

    发明人： Toshiro Hiramoto ,  Takayasu Sakurai ,  Makoto Suzuki

    IPC分类号： G05F1/10

    CPC分类号： G11C11/413

    摘要： The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.

    摘要翻译： 电压Vdd被设定为低于正常工作（步骤S100），然后对电源电压施加节点Vdd，接地电压施加节点Vss，半导体衬底和阱施加电压，使得相对 导通晶体管的栅极与半导体衬底或导通晶体管的栅极之间的高电压（步骤S110和S120）。 该处理完成导通的晶体管的阈值电压的上升，包括锁存电路的存储单元的多个晶体管之间的阈值电压的变化的减小以及存储单元的电压特性的改善 。

    Self-aligned row-by-row dynamic VDD SRAM
    2.
    发明申请
    Self-aligned row-by-row dynamic VDD SRAM 失效
    自对准逐行动态VDD SRAM

    公开(公告)号：US20060039182A1

    公开(公告)日：2006-02-23

    申请号：US11205466

    申请日：2005-08-16

    申请人： Takayasu Sakurai ,  Hiroshi Kawaguchi ,  Robert Fayez

    发明人： Takayasu Sakurai ,  Hiroshi Kawaguchi ,  Robert Fayez

    IPC分类号： G11C11/00

    CPC分类号： G11C11/413

    摘要： A memory cell array includes a plurality of memory cells arranged in a matrix form. A word line and a power supply line respectively are connected in common to the plurality of memory cells arranged in each row. A power supply line/word line control circuit is connected to each word line and each power supply line. In accessing the plurality of memory cells row by row, the control circuit raises the voltage of the power supply line and, after the voltage of the power supply line reaches the high voltage at all the positions, starts activation of the word line. On the other hand, in turning from the access state to the non-access state, the control circuit deactivates the word line and, after the voltage of the word line changes to the ground voltage at all the positions, changes the voltage of the power supply line to the low voltage.

    摘要翻译： 存储单元阵列包括以矩阵形式布置的多个存储单元。 字线和电源线分别连接到布置在每一行中的多个存储单元。 电源线/字线控制电路连接到每个字线和每个电源线。 在逐行访问多个存储单元时，控制电路提高电源线的电压，并且在所有位置的电源线的电压达到高电压之后，开始字线的激活。 另一方面，在从访问状态转到非访问状态时，控制电路使字线停止，并且在字线的电压在所有位置变化为接地电压之后，改变电源的电压 供电线路为低电压。

    ECL output buffer with a MOS transistor used for tristate enable
    3.
    发明授权
    ECL output buffer with a MOS transistor used for tristate enable 失效
    具有用于三态使能的MOS晶体管的ECL输出缓冲器

    公开(公告)号：US5434517A

    公开(公告)日：1995-07-18

    申请号：US215174

    申请日：1994-03-21

    申请人： Hiroyuki Hara ,  Takayasu Sakurai

    发明人： Hiroyuki Hara ,  Takayasu Sakurai

    IPC分类号： H03K19/08 ,  H03K19/018 ,  H03K19/082 ,  H03K19/086

    CPC分类号： H03K19/01812 ,  H03K19/0826

    摘要： An ECL output buffer circuit is constituted by an output buffer circuit main portion and its control circuit. In the output buffer circuit main portion, an output from a differential switch is input to the base of a bipolar transistor (emitter follower). The emitter of the bipolar transistor is connected to an output terminal. A ground potential is applied to the collector of the bipolar transistor. One end of the channel conductive path of a MOS transistor is connected to the base of the bipolar transistor. The other end of the channel conductive path is connected to a power-supply terminal via a constant-current source. The control circuit controls the ON/OFF operation of the MOS transistor and the output level of the bipolar transistor. When the output buffer circuit main portion is to be set in a standby state, the control circuit performs control to set the MOS transistor in an ON state and set the output of the bipolar transistor at low level.

    摘要翻译： ECL输出缓冲电路由输出缓冲电路主要部分及其控制电路构成。 在输出缓冲电路主要部分中，差分开关的输出被输入到双极晶体管（射极跟随器）的基极。 双极晶体管的发射极连接到输出端子。 接地电位施加到双极晶体管的集电极。 MOS晶体管的沟道导电路径的一端连接到双极晶体管的基极。 通道导电路径的另一端经由恒流源与电源端子连接。 控制电路控制MOS晶体管的ON / OFF操作和双极晶体管的输出电平。 当输出缓冲器电路主要部分被设置在待机状态时，控制电路进行控制以将MOS晶体管设置在导通状态，并将双极晶体管的输出设置为低电平。

    Semiconductor memory device having a function of simultaneously clearing part of memory data
    4.
    发明授权
    Semiconductor memory device having a function of simultaneously clearing part of memory data 失效
    具有同时清除部分存储器数据的功能的半导体存储器件

    公开(公告)号：US4958326A

    公开(公告)日：1990-09-18

    申请号：US274555

    申请日：1988-11-22

    申请人： Takayasu Sakurai

    发明人： Takayasu Sakurai

    IPC分类号： G11C11/401 ,  G11C7/20 ,  G11C8/12

    CPC分类号： G11C7/20 ,  G11C8/12

    摘要： A semiconductor memory device includes a first memory cell array and a second memory cell array section into which the same data can be simultaneously written. Logic gates are provided between the word lines of the first memory cell array section and the respective word lines of the second memory cell array section. In the normal operation mode, the logic gates connect each of the rows of memory cells in the first memory cell array section to a corresponding one of the rows of memory cells in the second memory cell array section, and set each of the rows of memory cells in the second memory cell array section to a selected level when the same data is simultaneously written into the memory cells of the second memory cell array section. When each of the rows of memory cells in the second memory cell array section is set to the selected level, all the columns of the memory cells in the second memory cell array section are simultaneously selected and the same data is simultaneously written into the second memory cell array section.

    Semiconductor memory cell
    5.
    发明授权
    Semiconductor memory cell 失效
    半导体存储单元

    公开(公告)号：US4905192A

    公开(公告)日：1990-02-27

    申请号：US175252

    申请日：1988-03-30

    申请人： Kazutaka Nogami ,  Takayasu Sakurai

    发明人： Kazutaka Nogami ,  Takayasu Sakurai

    IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/842

    摘要： A semiconductor memory device includes a memory cell array, a spare memory cell array, a first addressing circuit for designating an address of the memory cell array, a second addressing circuit for designating an address of the spare memory cell array, a drive circuit for activating a select line designated by each of the first and second addressing circuits, a program circuit for generating a predetermined output based on whether the memory cell array has a defect or fault or not, and a select circuit responsive to an output from the program circuit for supplying an activation signal to the designated select line at an earlier timing when there is no fault in the memory array cell, and supplying an activation signal delayed by a time necessary for the selection of the spare memory cell array when there is a fault in the memory cell array.

    摘要翻译： 半导体存储器件包括存储单元阵列，备用存储单元阵列，用于指定存储单元阵列的地址的第一寻址电路，用于指定备用存储单元阵列的地址的第二寻址电路，用于激活的驱动电路 由第一和第二寻址电路中的每一个指定的选择线，用于基于存储单元阵列是否具有缺陷或故障来产生预定输出的程序电路，以及响应于来自程序电路的输出的选择电路， 当存储器阵列单元中没有故障时，在更早的定时向指定的选择线提供激活信号，并且当存在故障时提供延迟了选择备用存储单元阵列所需的时间的激活信号 存储单元阵列。

    MOS semiconductor circuit
    6.
    发明授权
    MOS semiconductor circuit 失效
    MOS半导体电路

    公开(公告)号：US4853654A

    公开(公告)日：1989-08-01

    申请号：US72443

    申请日：1987-07-13

    申请人： Takayasu Sakurai

    发明人： Takayasu Sakurai

    IPC分类号： H03K5/05 ,  H03K3/011 ,  H03K3/354

    CPC分类号： H03K3/354 ,  H03K3/011

    摘要： An MOS semiconductor circuit includes cascade connected logical circuits. The MOS semiconductor circuit further includes an MOS transistor circuit having at least one first MOS transistor coupled between a source voltage terminal and the output node of the individual logical circuits, and a second MOS transistor, which has the same conductivity type as the first MOS transistor and has its gate and drain short-circuited, with this gate being coupled to the gate of the first MOS transistor. The MOS semiconductor circuit also includes a current control circuit, which is coupled to the drain of the second MOS transistor for providing a predetermined current between the source and drain of the second MOS transistor.

    摘要翻译： MOS半导体电路包括级联连接的逻辑电路。 MOS半导体电路还包括MOS晶体管电路，其具有耦合在各个逻辑电路的源极电压端子和输出节点之间的至少一个第一MOS晶体管，以及具有与第一MOS晶体管相同的导电类型的第二MOS晶体管 并且其栅极和漏极短路，该栅极耦合到第一MOS晶体管的栅极。 MOS半导体电路还包括电流控制电路，其耦合到第二MOS晶体管的漏极，用于在第二MOS晶体管的源极和漏极之间提供预定电流。

    Intermediate potential generating circuit
    7.
    发明授权
    Intermediate potential generating circuit 失效
    中间电位发生电路

    公开(公告)号：US4812735A

    公开(公告)日：1989-03-14

    申请号：US138798

    申请日：1987-12-28

    申请人： Kazuhiro Sawada ,  Takayasu Sakurai

    发明人： Kazuhiro Sawada ,  Takayasu Sakurai

    IPC分类号： G05F3/24 ,  G11C11/407 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  G05F3/30

    CPC分类号： G05F3/247

    摘要： This invention provides an intermediate potential generating circuit comprising a load element of which one end is connected to a first potential supply source, a first transistor of a first conductivity type of which one end and the gate thereof are connected to the other end of the load element, a second transistor of a second conductivity type of which one end is connected to the other end of the first transistor, and the gate and the other end thereof are connected together, a constant-voltage means connected between the other end of the second transistor and a second potential supply source for causing a specific voltage drop between the ends of the contant-voltage means, a third transistor of the first conductivity type of which one end is connected to the first potential supply source, the gate is connected to a node between the load element and the first transistor, and the other end thereof is connected to an output terminal, and a fourth transistor of the second conductivity type which is connected between the output terminal and the second supply source and of which the gate is connected to a node between the second transistor and the constant-voltage means.

    Semiconductor memory device capable of being accessed before completion of data output
    8.
    发明授权
    Semiconductor memory device capable of being accessed before completion of data output 失效
    能够在完成数据输出之前访问的半导体存储器件

    公开(公告)号：US4764901A

    公开(公告)日：1988-08-16

    申请号：US761709

    申请日：1985-08-02

    申请人： Takayasu Sakurai

    发明人： Takayasu Sakurai

    IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4096 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/065 ,  G11C11/406 ,  G11C11/4096 ,  G11C7/1051

    摘要： The semiconductor memory device contains a plurality of memory cells, a row decoder for selectively actuating memory cells according to the selected one of the row and column address signals, and bit lines set to a potential dependent on the data in the memory cell actuated. Particularly, this memory device has latching circuits for latching the potentials on the bit lines, and a timing controller for causing the latching circuits to keep the latched potentials for a predetermined period after the update of the row address signal.

    摘要翻译： 半导体存储器件包含多个存储器单元，行解码器，用于根据行和列地址信号中所选择的一个选择性地启动存储器单元，以及设置为依赖于致动的存储器单元中的数据的电位的位线。 特别地，该存储器件具有用于锁存位线上的电位的锁存电路，以及用于在更新行地址信号之后使锁存电路保持锁存电位达预定时间段的定时控制器。