公开(公告)号：US20110315853A1

公开(公告)日：2011-12-29

申请号：US13159540

申请日：2011-06-14

申请人： Kwang Jun CHO ,  Tae Woo KIM

发明人： Kwang Jun CHO ,  Tae Woo KIM

IPC分类号： H01L27/146

CPC分类号： H01L27/14605 ,  H01L27/14643 ,  H04N5/3696 ,  H04N5/3745

摘要： An image sensor includes a dummy pixel array with at least one dummy pixel, a pixel array with a plurality of main pixels, and a data processing unit configured to process a signal provided from the main pixels. The dummy pixel includes: a first switch having a first terminal receiving a first voltage and a second terminal coupled to a floating node; a second switch having a first terminal receiving a second voltage; a third switch coupled between a second terminal of the second switch and the floating node; and a driving element configured to drive a first terminal thereof according to a voltage level applied to the floating node.

摘要翻译： 图像传感器包括具有至少一个虚拟像素的虚拟像素阵列，具有多个主像素的像素阵列以及被配置为处理从主像素提供的信号的数据处理单元。 伪像素包括：第一开关，具有接收第一电压的第一端子和耦合到浮动节点的第二端子; 第二开关，具有接收第二电压的第一端子; 耦合在所述第二开关的第二端子和所述浮动节点之间的第三开关; 以及驱动元件，其被配置为根据施加到所述浮动节点的电压电平来驱动其第一端子。

公开(公告)号：US20120112041A1

公开(公告)日：2012-05-10

申请号：US13293367

申请日：2011-11-10

申请人： Kwang Jun CHO

发明人： Kwang Jun CHO

IPC分类号： H01L27/146

CPC分类号： H04N5/347

摘要： Provided is an image sensor including a plurality of sampling units, a plurality of signal lines connected to an amplification unit; and a plurality of first switches positioned between the plurality of sampling units and the plurality of signal lines, connecting a plurality of sampling units to the plurality of signal lines when performing analog binning operation, and connecting one of the plurality of sampling units to one of the signal lines when performing a general operation.

摘要翻译： 提供一种图像传感器，包括多个采样单元，多个信号线连接到放大单元; 以及位于所述多个采样单元和所述多个信号线之间的多个第一开关，当进行模拟合并操作时，将多个采样单元连接到所述多条信号线，并将所述多个采样单元之一连接到 执行一般操作时的信号线。

公开(公告)号：US20090161455A1

公开(公告)日：2009-06-25

申请号：US12199046

申请日：2008-08-27

申请人： Kie Bong KU ,  Kwang Jun CHO

发明人： Kie Bong KU ,  Kwang Jun CHO

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/225 ,  G11C8/06 ,  G11C8/18

摘要： In the data input apparatus, a data delay unit outputs data input from outside the data input apparatice. The data delay unit varies the degree of delay in response to a test mode signal. A data alignment signal generating unit receives a first signal synchronized with an external clock signal and a second signal synchronized with a data strobe signal, and the data alignment signal generating unit outputs one of the first signal and the second signal as a data alignment signal in response to the test mode signal. A data alignment unit is synchronized with the data alignment signal to align the data delayed in the data delay unit. The data input apparatus improves the setup/hold window when a semiconductor memory device is in the test mode.

摘要翻译： 在数据输入装置中，数据延迟单元输出从数据输入装置外部输入的数据。 数据延迟单元改变响应于测试模式信号的延迟程度。 数据对准信号发生单元接收与外部时钟信号同步的第一信号和与数据选通信号同步的第二信号，数据对准信号生成单元将第一信号和第二信号中的一个作为数据对准信号输出 响应测试模式信号。 数据对准单元与数据对准信号同步，以对准在数据延迟单元中延迟的数据。 当半导体存储器件处于测试模式时，数据输入设备改进了建立/保持窗口。

公开(公告)号：US20080284478A1

公开(公告)日：2008-11-20

申请号：US12184363

申请日：2008-08-01

申请人： Kwang Jun CHO

发明人： Kwang Jun CHO

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： The present invention relates to a duty correction circuit that corrects a distorted duty of a clock signal using a delay unit and a delay controller, thereby reducing the layout area and current consumption. The duty correction circuit includes a repeater that generates a clock signal having the same phase as that of an input clock signal with a distorted duty, and a clock signal having an inverted phase of the phase; a delay line delaying the phase of the clock signal having the inverted phase and generating a feedback clock signal; a phase comparator comparing the phase of the clock signal having the same phase with the phase of the feedback clock signal and generating a delay control signal according to the phase difference between the phases of the clock signal having he same phase and the feedback clock signal; a delay controller controlling the amount of delay of the delay line according to the delay control signal; and a phase mixer performing half-phase blending on the clock signal having the same phase and the feedback clock signal and outputting a clock signal having a corrected duty.

摘要翻译： 本发明涉及一种使用延迟单元和延迟控制器校正时钟信号的失真占空比的占空比校正电路，从而减少布局面积和电流消耗。 该占空比校正电路包括一个中继器，它产生与具有失真占空比的输入时钟信号具有相同相位的时钟信号，以及一个具有该相位的相位相位的时钟信号; 延迟线延迟具有反相的时钟信号的相位并产生反馈时钟信号; 相位比较器，将具有相同相位的时钟信号的相位与反馈时钟信号的相位进行比较，并根据具有相同相位的时钟信号的相位与反馈时钟信号之间的相位差产生延迟控制信号; 延迟控制器控制根据延迟控制信号的延迟线路的延迟量; 和相位混频器进行半相共混上具有相同相位和反馈时钟信号和输出具有占空比校正的时钟信号的时钟信号。

公开(公告)号：US20080272812A1

公开(公告)日：2008-11-06

申请号：US12174000

申请日：2008-07-16

申请人： Kwang Jun CHO

发明人： Kwang Jun CHO

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  G11C7/22 ,  G11C7/222

摘要： A delay-locked-loop control circuit and a method of controlling a delay-locked-loop. When the delay-locked-loop is in an off-operation mode, such as a power-down mode, a self-refresh emulation mode, a self-refresh mode, and the like, the delay-locked-loop is updated with a predetermined period, thereby preventing a malfunction of the delay-locked-loop. The delay-locked-loop has an oscillating portion which generates an oscillation signal having a predetermined period when in an OFF state; a pulse generating portion which generates a pulse signal having a predetermined period using the oscillation signal; a dividing portion which divides the pulse signal to generate a delay-locked-loop update signal; and a combining portion which combines the delay-locked-loop update signal and a delay-locked-loop on signal that is enabled by an external command to generate a delay-locked-loop control signal for controlling the delay-locked-loop.

摘要翻译： 延迟锁定环控制电路和控制延迟锁定环路的方法。 当延迟锁定环处于诸如掉电模式，自刷新仿真模式，自刷新模式等的关闭操作模式时，延迟锁定环被更新为 从而防止延迟锁定环路的故障。 延迟锁定环具有振荡部，其在处于断开状态时产生具有预定周期的振荡信号; 脉冲发生部分，利用振荡信号产生具有预定周期的脉冲信号; 分割部分，其分割脉冲信号以产生延迟锁定环更新信号; 以及组合部分，其组合延迟锁定环更新信号和由外部命令启用的延迟锁定环路信号，以产生用于控制延迟锁定环路的延迟锁定环控制信号。

公开(公告)号：US20130032691A1

公开(公告)日：2013-02-07

申请号：US13412832

申请日：2012-03-06

申请人： Kwang Jun CHO

发明人： Kwang Jun CHO

IPC分类号： G01J1/46 ,  G01J1/44

CPC分类号： G01J1/44 ,  H01L27/14609 ,  H01L27/14612 ,  H04N5/3575

摘要： An image sensor for reducing a sampling time by shortening a stabilization duration is provided. The image sensor includes a pixel unit, a sampling unit sampling a signal from an output node of the pixel unit, a sinking unit sinking current from the output node of the pixel unit, and a current controller controlling the amount of current in the sinking unit.

摘要翻译： 提供了一种用于通过缩短稳定持续时间来减少采样时间的图像传感器。 图像传感器包括像素单元，对来自像素单元的输出节点的信号进行采样的采样单元，从像素单元的输出节点吸收电流的吸收单元和控制下沉单元中的电流量的电流控制器 。

公开(公告)号：US20120112040A1

公开(公告)日：2012-05-10

申请号：US13293344

申请日：2011-11-10

申请人： Kwang Jun CHO

发明人： Kwang Jun CHO

IPC分类号： H01L27/146

CPC分类号： H04N5/3742 ,  H01L27/14609 ,  H04N5/347

摘要： There is provided an image sensor, including an input control unit configured to control signal paths between a plurality of pixels and a plurality of sampling units and supplying outputs from the plurality of pixels in row units to the plurality of sampling units during a normal operation, while supplying the outputs from the plurality of pixels by color, to the plurality of sampling units during a binning operation; and an output control unit configured to control signal paths between the plurality of sampling units and an amplification unit and sequentially supplying outputs from the plurality of sampling units to the amplification unit during the normal operation while simultaneously supplying the outputs from the plurality of sampling units to the amplification unit during the binning operation.

摘要翻译： 提供了一种图像传感器，包括：输入控制单元，被配置为控制多个像素与多个采样单元之间的信号路径，并且在正常操作期间以行为单位将多个像素的输出提供给多个采样单元; 同时在合并操作期间将多个像素的输出提供给多个采样单元; 以及输出控制单元，被配置为控制所述多个采样单元和放大单元之间的信号路径，并且在正常操作期间顺序地将来自所述多个采样单元的输出提供给所述放大单元，同时将来自所述多个采样单元的输出提供给 在合并操作期间的放大单元。

公开(公告)号：US20110181328A1

公开(公告)日：2011-07-28

申请号：US13083247

申请日：2011-04-08

申请人： Kwang Jun CHO ,  Jun Hyun Chun

发明人： Kwang Jun CHO ,  Jun Hyun Chun

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： A frequency adjusting apparatus includes a frequency control signal generating unit that generates a multi-bit frequency control signal, which is changed in level bit by bit, in response to a reference clock signal, and a frequency adjusting unit that adjusts the frequency of the reference clock signal in response to the multi-bit frequency control signal.

摘要翻译： 一种频率调整装置，包括：频率控制信号生成部，其响应于基准时钟信号，生成逐位变化的多位频率控制信号;以及频率调整部，其调整基准的频率 响应于多位频率控制信号的时钟信号。

公开(公告)号：US20070247203A1

公开(公告)日：2007-10-25

申请号：US11687396

申请日：2007-03-16

申请人： Kwang Jun CHO ,  Kie Bong KU

发明人： Kwang Jun CHO ,  Kie Bong KU

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： The digital duty cycle correction circuit according to the present invention includes a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a capacitor, converting the delayed second clock into a first signal, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of the first signal; and a second conversion circuit for converting the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock.

摘要翻译： 根据本发明的数字占空比校正电路包括用于缓冲来自延迟锁定环（DLL）的内部时钟输出的第一转换电路，通过第一和第二终端将缓冲的内部时钟转换成第一和第二时钟，延迟第二 时钟，根据通过电容器提供给第二终端的电压，将延迟的第二时钟转换为第一信号，并将第一时钟转换为第三时钟，第三时钟在第一时钟的下降沿上升，并且下降到 第一个信号; 以及第二转换电路，用于将第三时钟转换为在第三时钟的下降沿上升并在第三时钟的上升沿下降的输出时钟。

公开(公告)号：US20090195283A1

公开(公告)日：2009-08-06

申请号：US12421434

申请日：2009-04-09

申请人： Kwang Jun CHO ,  Kie Bong KU

发明人： Kwang Jun CHO ,  Kie Bong KU

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： The digital duty cycle correction circuit according to the present invention includes a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a capacitor, converting the delayed second clock into a first signal, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of the first signal; and a second conversion circuit for converting the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock.

摘要翻译： 根据本发明的数字占空比校正电路包括用于缓冲来自延迟锁定环（DLL）的内部时钟输出的第一转换电路，通过第一和第二终端将缓冲的内部时钟转换成第一和第二时钟，延迟第二 时钟，根据通过电容器提供给第二终端的电压，将延迟的第二时钟转换为第一信号，并将第一时钟转换为第三时钟，第三时钟在第一时钟的下降沿上升，并且下降到 第一个信号; 以及第二转换电路，用于将第三时钟转换为在第三时钟的下降沿上升并在第三时钟的上升沿下降的输出时钟。