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1.发明申请公开(公告)号：US20090321344A1
公开(公告)日：2009-12-31
申请号：US12486112
申请日：2009-06-17
Applicant: Kwang-Jin LEE , Moo-Seok LEE , Yong-Cheol SHIN
Inventor： Kwang-Jin LEE , Moo-Seok LEE , Yong-Cheol SHIN
CPC classification number: B01D63/02 , B01D2313/21
Abstract: A header for filtering membrane module and a filtering membrane module using the same is disclosed, which is capable of maximizing efficiency in power consumption by securing a constant flow of permeate through the use of a relatively-low negative pressure, the header for filtering membrane module comprising a body with a permeate collecting space therein; and a conduit at one end of the body, the conduit being in fluid communication with the permeate collecting space, wherein at least a portion of the permeate collecting space has an inclined shape.
Abstract translation: 公开了用于过滤膜组件的头部和使用其的过滤膜组件，其能够通过使用相对低的负压确保渗透物的恒定流量来最大化功率消耗的效率，用于过滤膜组件 包括其中具有渗透物收集空间的主体; 以及在所述主体的一端处的导管，所述导管与所述渗透物收集空间流体连通，其中所述渗透物收集空间的至少一部分具有倾斜形状。
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公开(公告)号：US20110170334A1
公开(公告)日：2011-07-14
申请号：US13053471
申请日：2011-03-22
Applicant: Joon-Min PARK , Kwang-Jin LEE , Du-Eung KIM , Woo-Yeong CHO , Hui-Kwon SEO
Inventor： Joon-Min PARK , Kwang-Jin LEE , Du-Eung KIM , Woo-Yeong CHO , Hui-Kwon SEO
CPC classification number: G11C13/0069 , G11C13/0004 , G11C2213/72
Abstract: Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using an internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.
Abstract translation: 提供了一种非易失性存储器及其相关编程方法。 非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。 写电路被配置为在第一程序操作期间使用内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二程序操作期间将第二逻辑状态数据写入第二组存储器单元 外部提供的升压电压。
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3.发明申请APPARATUS AND METHOD OF NONVOLATILE MEMORY DEVICE HAVING THREE-LEVEL NONVOLATILE MEMORY CELLS 有权具有三级非易失性记忆细胞的非易失性记忆装置的装置和方法公开(公告)号：US20090046500A1
公开(公告)日：2009-02-19
申请号：US12187550
申请日：2008-08-07
Applicant: Kwang-Jin LEE , Du-Eung KIM , Woo-Yeong CHO
Inventor： Kwang-Jin LEE , Du-Eung KIM , Woo-Yeong CHO
CPC classification number: G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0071 , G11C2013/0078 , G11C2013/0092 , G11C2211/5622 , G11C2211/5641 , G11C2213/72 , G11C2213/79
Abstract: An apparatus and operating method of a nonvolatile memory device having three-level nonvolatile memory cells is used to store more than one bit of data in a nonvolatile memory cell. In addition, the data can be selectively written through a write-verify operation, thereby improving write operation reliability. The operating method includes providing a memory cell array having first through third nonvolatile memory cells where each memory cell is capable of storing one among first data through third data corresponding to first through third resistance levels, respectively. Each of the resistance levels is different from one another. First and the third data are written to the first and third nonvolatile memory cells, respectively, during a first interval of a write operation. Second data is written to the second nonvolatile memory cell during a second interval of the write operation.
Abstract translation: 使用具有三电平非易失性存储单元的非易失性存储器件的装置和操作方法在非易失性存储单元中存储多于一位的数据。 此外，可以通过写入验证操作来选择性地写入数据，从而提高写入操作的可靠性。 操作方法包括提供具有第一至第三非易失性存储单元的存储单元阵列，其中每个存储单元能够分别在第一数据与第一至第三电阻电平对应的第三数据之间存储一个存储单元。 每个阻力水平彼此不同。 在写入操作的第一间隔期间，分别将第一和第三数据写入第一和第三非易失性存储器单元。 在写入操作的第二间隔期间，将第二数据写入第二非易失性存储单元。
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公开(公告)号：US20080144363A1
公开(公告)日：2008-06-19
申请号：US11953146
申请日：2007-12-10
Applicant: Chang-Soo LEE , Hyung-Rok OH , Beak-Hyung CHO , Kwang-Jin LEE
Inventor： Chang-Soo LEE , Hyung-Rok OH , Beak-Hyung CHO , Kwang-Jin LEE
CPC classification number: G11C29/08 , G11C13/0004
Abstract: A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.
Abstract translation: 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。
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公开(公告)号：US20100232218A1
公开(公告)日：2010-09-16
申请号：US12787571
申请日：2010-05-26
Applicant: Chang-Soo LEE , Hyung-Rok OH , Beak-Hyung CHO , Kwang-Jin LEE
Inventor： Chang-Soo LEE , Hyung-Rok OH , Beak-Hyung CHO , Kwang-Jin LEE
CPC classification number: G11C29/08 , G11C13/0004
Abstract: A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.
Abstract translation: 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。
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Patent Agency Ranking
公开(公告)号：US20100124105A1
公开(公告)日：2010-05-20
申请号：US12693005
申请日：2010-01-25
Applicant: Qi WANG , Kwang-Jin LEE , Woo-Yeong CHO , Taek-Sung KIM , Kwang-Ho KIM , Hyun-Ho CHOI , Yong-Jun LEE , Hye-Jin KIM
Inventor： Qi WANG , Kwang-Jin LEE , Woo-Yeong CHO , Taek-Sung KIM , Kwang-Ho KIM , Hyun-Ho CHOI , Yong-Jun LEE , Hye-Jin KIM
CPC classification number: G11C8/12 , G11C11/005 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C16/0483 , G11C2013/0078 , G11C2213/71
Abstract: Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.
Abstract translation: 公开了一种半导体存储器件，包括具有分成第一和第二区域的多个可变电阻存储器单元的存储单元阵列。 I / O电路被配置为在控制逻辑的控制下访问存储单元阵列，以响应于外部命令访问第一或第二区域。 I / O电路使用存储单元单元访问第一区域，并且使用页面单元访问第二区域。
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7.发明申请METHOD OF DRIVING MULTI-LEVEL VARIABLE RESISTIVE MEMORY DEVICE AND MULTI-LEVEL VARIABLE RESISTIVE MEMORY DEVICE 有权驱动多级可变电阻记忆装置和多级可变电阻记忆装置的方法公开(公告)号：US20100085799A1
公开(公告)日：2010-04-08
申请号：US12632018
申请日：2009-12-07
Applicant: Woo-Yeong CHO , Ki-Sung KIM , Du-Eung KIM , Kwang-Jin LEE , Jun-Soo BAE
Inventor： Woo-Yeong CHO , Ki-Sung KIM , Du-Eung KIM , Kwang-Jin LEE , Jun-Soo BAE
CPC classification number: G11C11/5678 , G11C7/04 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0078 , G11C2211/5634
Abstract: Disclosed is a method of driving a multi-level variable resistive memory device. A method of driving a multi-level variable resistive memory device includes supplying a write current to a variable resistive memory cell so as to change resistance of the variable resistive memory cell, verifying whether or not changed resistance enters a predetermined resistance window, the intended resistance window depending on the resistance of reference cells, and supplying a write current having an increased or decreased amount from the write current supplied most recently on the basis of the verification result so as to change resistance of the variable resistive memory cell.
Abstract translation: 公开了一种驱动多电平可变电阻存储器件的方法。 驱动多电平可变电阻存储器件的方法包括向可变电阻存储器单元提供写入电流，以便改变可变电阻存储器单元的电阻，验证改变的电阻是否进入预定的电阻窗，预期电阻 窗口，取决于参考单元的电阻，并且基于验证结果从最近提供的写入电流提供具有增加或减少的量的写入电流，以便改变可变电阻存储单元的电阻。
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8.发明申请Content addressable memory cell and content addressable memory using phase change memory 失效内容可寻址存储单元和内容可寻址存储器，使用相变存储器公开(公告)号：US20080068872A1
公开(公告)日：2008-03-20
申请号：US11892851
申请日：2007-08-28
Applicant: Kwang-Jin LEE , Du-eung KIM
Inventor： Kwang-Jin LEE , Du-eung KIM
IPC: G11C15/00
CPC classification number: G11C15/046 , G11C13/0004
Abstract: According to an example embodiment, a CAM cell included in a CAM may include a phase change memory device, a connector, and/or a developer. The phase change memory device may be configured to store data. The phase change memory device may have a resistance that may be varied according to the logic level of the stored data. The connector may be configured to control writing data to the phase change memory device and reading data from the phase change memory device. The developer may be configured to control reading data from the phase change memory device in a search mode in which the data stored in the phase change memory device is compared to the search data.
Abstract translation: 根据示例实施例，CAM中包括的CAM单元可以包括相变存储器件，连接器和/或显影器。 相变存储器件可以被配置为存储数据。 相变存储器件可以具有可以根据存储的数据的逻辑电平而改变的电阻。 连接器可以被配置为控制向相变存储器件写入数据并从相变存储器件读取数据。 开发者可以被配置为在存储在相变存储器件中的数据与搜索数据进行比较的搜索模式中控制从相变存储器件读取数据。
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9.发明申请公开(公告)号：US20100008133A1
公开(公告)日：2010-01-14
申请号：US12559792
申请日：2009-09-15
Applicant: Woo-Yeong CHO , Kwang-Jin LEE , Hye-Jin KIM
Inventor： Woo-Yeong CHO , Kwang-Jin LEE , Hye-Jin KIM
CPC classification number: G11C8/10 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/0076 , G11C2013/0078
Abstract: A method of writing data in a phase change memory includes; receiving write data to be written to a selected phase change memory cell in the plurality of phase change memory cells, sensing data stored in the selected phase change memory cell, determining whether or not the sensed data is equal to the write data, and if the sensed data is not equal to the write data, iteratively applying a write current to the selected phase change memory cell, wherein a resistance state of the phase change memory cell is changed by heat corresponding to a level of the write current, and the level of the write current is changed between successive iterative applications.
Abstract translation: 在相变存储器中写入数据的方法包括： 接收要写入所述多个相变存储单元中的所选择的相变存储单元的写入数据，感测存储在所选择的相变存储单元中的数据，确定所感测的数据是否等于写入数据，以及如果 感测数据不等于写数据，对所选择的相变存储单元迭代地施加写入电流，其中相变存储单元的电阻状态根据与写入电流的电平相对应的热量而改变， 写入电流在连续的迭代应用程序之间改变。
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10.发明申请公开(公告)号：US20090161421A1
公开(公告)日：2009-06-25
申请号：US12395999
申请日：2009-03-02
Applicant: Woo-Yeong CHO , Kwang-Jin LEE , Hye-Jin KIM
Inventor： Woo-Yeong CHO , Kwang-Jin LEE , Hye-Jin KIM
IPC: G11C11/00 , G11C11/416
CPC classification number: G11C8/10 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/0076 , G11C2013/0078
Abstract: A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.
Abstract translation: 相变存储器件通过接收在所选择的存储器单元中被编程的程序数据来执行编程操作，当检验读取电压为检测电压时，通过检测流过选择的存储器单元的检验电流的大小来感测已经存储在所选存储单元中的读取数据 应用于所选择的存储单元，确定读取的数据是否与程序数据相同，并且在确定所选择的存储单元中的一个或多个的程序数据与相应的读取数据不相同时，编程所选择的一个或多个 存储单元与程序数据。
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