中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.051 seconds)

    PHASE CHANGE MEMORY DEVICES AND SYSTEMS, AND RELATED PROGRAMMING METHODS
    2.
    发明申请
    PHASE CHANGE MEMORY DEVICES AND SYSTEMS, AND RELATED PROGRAMMING METHODS 有权
    相变存储器件和系统以及相关编程方法

    公开(公告)号：US20100008133A1

    公开(公告)日：2010-01-14

    申请号：US12559792

    申请日：2009-09-15

    Applicant: Woo-Yeong CHO ,  Kwang-Jin LEE ,  Hye-Jin KIM

    Inventor： Woo-Yeong CHO ,  Kwang-Jin LEE ,  Hye-Jin KIM

    IPC: G11C11/00 ,  G11C7/10 ,  G11C7/06 ,  G11C7/00

    CPC classification number: G11C8/10 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078

    Abstract: A method of writing data in a phase change memory includes; receiving write data to be written to a selected phase change memory cell in the plurality of phase change memory cells, sensing data stored in the selected phase change memory cell, determining whether or not the sensed data is equal to the write data, and if the sensed data is not equal to the write data, iteratively applying a write current to the selected phase change memory cell, wherein a resistance state of the phase change memory cell is changed by heat corresponding to a level of the write current, and the level of the write current is changed between successive iterative applications.

    Abstract translation: 在相变存储器中写入数据的方法包括： 接收要写入所述多个相变存储单元中的所选择的相变存储单元的写入数据，感测存储在所选择的相变存储单元中的数据，确定所感测的数据是否等于写入数据，以及如果 感测数据不等于写数据，对所选择的相变存储单元迭代地施加写入电流，其中相变存储单元的电阻状态根据与写入电流的电平相对应的热量而改变， 写入电流在连续的迭代应用程序之间改变。

    PHASE CHANGE MEMORY DEVICES AND SYSTEMS, AND RELATED PROGRAMMING METHODS
    3.
    发明申请
    PHASE CHANGE MEMORY DEVICES AND SYSTEMS, AND RELATED PROGRAMMING METHODS 有权
    相变存储器件和系统以及相关编程方法

    公开(公告)号：US20090161421A1

    公开(公告)日：2009-06-25

    申请号：US12395999

    申请日：2009-03-02

    Applicant: Woo-Yeong CHO ,  Kwang-Jin LEE ,  Hye-Jin KIM

    Inventor： Woo-Yeong CHO ,  Kwang-Jin LEE ,  Hye-Jin KIM

    IPC: G11C11/00 ,  G11C11/416

    CPC classification number: G11C8/10 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078

    Abstract: A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.

    Abstract translation: 相变存储器件通过接收在所选择的存储器单元中被编程的程序数据来执行编程操作，当检验读取电压为检测电压时，通过检测流过选择的存储器单元的检验电流的大小来感测已经存储在所选存储单元中的读取数据 应用于所选择的存储单元，确定读取的数据是否与程序数据相同，并且在确定所选择的存储单元中的一个或多个的程序数据与相应的读取数据不相同时，编程所选择的一个或多个 存储单元与程序数据。

    NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE MATERIALS
    5.
    发明申请
    NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE MATERIALS 审中-公开
    使用可变电阻材料的非易失性存储器件

    公开(公告)号：US20080291715A1

    公开(公告)日：2008-11-27

    申请号：US12116295

    申请日：2008-05-07

    Applicant: Mu-Hui PARK ,  Kwang-Jin LEE ,  Du-Eung KIM ,  Hye-Jin KIM ,  Woo-Yeong CHO

    Inventor： Mu-Hui PARK ,  Kwang-Jin LEE ,  Du-Eung KIM ,  Hye-Jin KIM ,  Woo-Yeong CHO

    IPC: G11C11/00 ,  G11C7/00

    CPC classification number: G11C13/0038 ,  G11C7/04 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028

    Abstract: A nonvolatile memory device includes a nonvolatile memory cell, a read circuit and a control bias generating circuit. The nonvolatile memory cell has a resistance level that changes depending on stored data. The read circuit reads the resistance level of the nonvolatile memory cell by receiving a control bias and supplying the nonvolatile memory cell a read bias based on the control bias. The control bias generating circuit receives an input bias, generates the control bias based on the input bias and supplies the control bias to the read circuit. A slope of the control bias to the input bias is less than 1.

    Abstract translation: 非易失性存储器件包括非易失性存储单元，读取电路和控制偏置产生电路。 非易失性存储单元具有根据存储的数据而改变的电阻水平。 读取电路通过接收控制偏置来读取非易失性存储单元的电阻电平，并且基于控制偏压向非易失性存储单元提供读取偏置。 控制偏置产生电路接收输入偏置，基于输入偏置产生控制偏压，并将控制偏压提供给读取电路。 对输入偏置的控制偏置的斜率小于1。

    BIAS VOLTAGE GENERATOR AND METHOD GENERATING BIAS VOLTAGE FOR SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    BIAS VOLTAGE GENERATOR AND METHOD GENERATING BIAS VOLTAGE FOR SEMICONDUCTOR MEMORY DEVICE 有权
    偏置电压发生器和生成半导体存储器件的偏置电压的方法

    公开(公告)号：US20080159017A1

    公开(公告)日：2008-07-03

    申请号：US11955562

    申请日：2007-12-13

    Applicant: Hye-Jin KIM ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Mu-Hui PARK

    Inventor： Hye-Jin KIM ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Mu-Hui PARK

    IPC: G11C5/14

    CPC classification number: G11C13/004 ,  G11C5/147 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C16/30 ,  G11C2013/0054 ,  G11C2213/72

    Abstract: There are provided a bias voltage generator, a semiconductor memory device having the bias voltage generator, and a method for generating the bias voltage. The bias voltage generator which generates the bias voltage to control a sensing current supplied to a memory cell for sensing data is characterized in that the bias voltage is output in response to an input voltage being applied, so that a slope of the bias voltage to the input voltage is different in at least two sections divided corresponding to a level of the input voltage.

    Abstract translation: 提供了偏置电压发生器，具有偏置电压发生器的半导体存储器件以及用于产生偏置电压的方法。 产生用于控制提供给存储单元的感测电流以感测数据的偏置电压的偏置电压发生器的特征在于，响应于所施加的输入电压而输出偏置电压，使得偏置电压的斜率 至少两个部分的输入电压不同，对应于输入电压的电平。

    NONVOLATILE MEMORY, MEMORY SYSTEM, AND METHOD OF DRIVING
    7.
    发明申请
    NONVOLATILE MEMORY, MEMORY SYSTEM, AND METHOD OF DRIVING 有权
    非易失性存储器，存储器系统和驱动方法

    公开(公告)号：US20110170334A1

    公开(公告)日：2011-07-14

    申请号：US13053471

    申请日：2011-03-22

    Applicant: Joon-Min PARK ,  Kwang-Jin LEE ,  Du-Eung KIM ,  Woo-Yeong CHO ,  Hui-Kwon SEO

    Inventor： Joon-Min PARK ,  Kwang-Jin LEE ,  Du-Eung KIM ,  Woo-Yeong CHO ,  Hui-Kwon SEO

    IPC: G11C11/00 ,  G11C11/14

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2213/72

    Abstract: Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using an internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

    Abstract translation: 提供了一种非易失性存储器及其相关编程方法。 非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。 写电路被配置为在第一程序操作期间使用内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二程序操作期间将第二逻辑状态数据写入第二组存储器单元 外部提供的升压电压。

    APPARATUS AND METHOD OF NONVOLATILE MEMORY DEVICE HAVING THREE-LEVEL NONVOLATILE MEMORY CELLS
    8.
    发明申请
    APPARATUS AND METHOD OF NONVOLATILE MEMORY DEVICE HAVING THREE-LEVEL NONVOLATILE MEMORY CELLS 有权
    具有三级非易失性记忆细胞的非易失性记忆装置的装置和方法

    公开(公告)号：US20090046500A1

    公开(公告)日：2009-02-19

    申请号：US12187550

    申请日：2008-08-07

    Applicant: Kwang-Jin LEE ,  Du-Eung KIM ,  Woo-Yeong CHO

    Inventor： Kwang-Jin LEE ,  Du-Eung KIM ,  Woo-Yeong CHO

    IPC: G11C11/00 ,  G11C7/00

    CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2211/5622 ,  G11C2211/5641 ,  G11C2213/72 ,  G11C2213/79

    Abstract: An apparatus and operating method of a nonvolatile memory device having three-level nonvolatile memory cells is used to store more than one bit of data in a nonvolatile memory cell. In addition, the data can be selectively written through a write-verify operation, thereby improving write operation reliability. The operating method includes providing a memory cell array having first through third nonvolatile memory cells where each memory cell is capable of storing one among first data through third data corresponding to first through third resistance levels, respectively. Each of the resistance levels is different from one another. First and the third data are written to the first and third nonvolatile memory cells, respectively, during a first interval of a write operation. Second data is written to the second nonvolatile memory cell during a second interval of the write operation.

    Abstract translation: 使用具有三电平非易失性存储单元的非易失性存储器件的装置和操作方法在非易失性存储单元中存储多于一位的数据。 此外，可以通过写入验证操作来选择性地写入数据，从而提高写入操作的可靠性。 操作方法包括提供具有第一至第三非易失性存储单元的存储单元阵列，其中每个存储单元能够分别在第一数据与第一至第三电阻电平对应的第三数据之间存储一个存储单元。 每个阻力水平彼此不同。 在写入操作的第一间隔期间，分别将第一和第三数据写入第一和第三非易失性存储器单元。 在写入操作的第二间隔期间，将第二数据写入第二非易失性存储单元。

    VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM
    10.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM 有权
    可变电阻存储器件和系统

    公开(公告)号：US20090251954A1

    公开(公告)日：2009-10-08

    申请号：US12417679

    申请日：2009-04-03

    Applicant: Qi WANG ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Taek-Sung KIM ,  Kwang-Ho KIM ,  Hyun-Ho CHOI

    Inventor： Qi WANG ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Taek-Sung KIM ,  Kwang-Ho KIM ,  Hyun-Ho CHOI

    IPC: G11C11/00 ,  G11C8/00 ,  G11C11/416

    CPC classification number: G11C16/08 ,  G11C8/12

    Abstract: Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.

    Abstract translation: 公开了一种半导体存储器件，包括具有分成第一和第二区域的多个可变电阻存储器单元的存储单元阵列。 I / O电路被配置为在控制逻辑的控制下访问存储单元阵列，以响应于外部命令访问第一或第二区域。 I / O电路使用存储单元单元访问第一区域，并且使用页面单元访问第二区域。

Patent Agency Ranking