公开(公告)号：US20110110176A1

公开(公告)日：2011-05-12

申请号：US12824882

申请日：2010-06-28

Applicant: Kyong Ha LEE ,  Joo Hyeon LEE

Inventor： Kyong Ha LEE ,  Joo Hyeon LEE

IPC: G11C8/10 ,  G11C8/06

CPC classification number: G11C11/408 ,  G11C7/1018 ,  G11C7/1066 ,  G11C2207/2227

Abstract: An address control circuit is presented for use in reducing a skew in a write operation mode. The address control circuit includes a read column address control circuit and a write column address control circuit. The read column address control circuit is configured to generate a read column address from an address during a first burst period for a read operation mode. The write column address control circuit is configured to generate a write column address from the address during a second burst period for a write operation mode.

Abstract translation: 呈现地址控制电路用于减少写操作模式中的偏斜。 地址控制电路包括读列地址控制电路和写列地址控制电路。 读列地址控制电路被配置为在读操作模式的第一突发时段期间从地址生成读列地址。 写列地址控制电路被配置为在写操作模式的第二突发周期期间从地址生成写列地址。

公开(公告)号：US20100157717A1

公开(公告)日：2010-06-24

申请号：US12493755

申请日：2009-06-29

Applicant: Kyong Ha LEE

Inventor： Kyong Ha LEE

IPC: G11C8/00 ,  G11C8/18 ,  G11C7/00

CPC classification number: G11C7/222 ,  G11C7/1027 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C8/04 ,  G11C8/10

Abstract: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.

Abstract translation: 半导体集成电路包括命令解码器，移位寄存器单元和命令地址锁存单元。 命令解码器响应于定义写入和读取模式的外部命令，并且被配置为使用上升或下降时钟根据外部命令提供写入命令或读取命令。 移位寄存器单元被配置为响应写入命令将外部地址和写入命令移位写入延迟。 列地址锁存单元被配置为在读取模式下锁存并提供外部地址作为列地址，并锁存从移位寄存器单元提供的写入地址，并将写入地址作为列地址提供给 写模式。

公开(公告)号：US20110128811A1

公开(公告)日：2011-06-02

申请号：US12826906

申请日：2010-06-30

Applicant: Kyong Ha LEE

Inventor： Kyong Ha LEE

IPC: G11C8/18

CPC classification number: G11C7/1018 ,  G11C7/1039 ,  G11C11/4076

Abstract: The internal command generation circuit includes a burst pulse generation unit and a pulse shifting unit. The burst pulse generation unit is configured to receive a command for a read or write operation, and generate a first burst pulse. The pulse shifting unit is configured to shift the first burst pulse and generate an internal command.

Abstract translation: 内部命令生成电路包括脉冲串脉冲发生单元和脉冲移位单元。 突发脉冲发生单元被配置为接收用于读取或写入操作的命令，并且生成第一突发脉冲。 脉冲移位单元被配置为移位第一突发脉冲并产生内部命令。

公开(公告)号：US20110075502A1

公开(公告)日：2011-03-31

申请号：US12648774

申请日：2009-12-29

Applicant: Kyong Ha LEE

Inventor： Kyong Ha LEE

IPC: G11C8/00

CPC classification number: G11C11/4087 ,  G11C2207/107

Abstract: The bank active signal generation circuit comprises a decoded signal generator and an active signal generator. The decoded signal generator generates decoded signals from a first bank access signal, a second bank access signal and a row address signal in response to when a prefetch signal at a first mode. The decoded signal generator also generates decoded signals from the first bank access signal, the second bank access signal, and a third bank access signal in response when the prefetch signal at a second mode. The active signal generator generates bank active signals in response to receiving the decoded signals, an active pulse and a precharge pulse.

Abstract translation: 存储体活动信号发生电路包括解码信号发生器和有源信号发生器。 解码信号发生器响应于何时处于第一模式的预取信号，从第一存储体存取信号，第二存​​储体存取信号和行地址信号产生解码信号。 当处于第二模式的预取信号时，解码信号发生器还产生来自第一存储体存取信号，第二存​​储体存取信号和第三存储体存取信号的解码信号。 响应于接收到解码信号，有效脉冲和预充电脉冲，有源信号发生器产生存储体有效信号。

公开(公告)号：US20130223160A1

公开(公告)日：2013-08-29

申请号：US13591306

申请日：2012-08-22

Applicant: Kyong Ha LEE

Inventor： Kyong Ha LEE

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C7/1084 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222

Abstract: A semiconductor memory device including a first edge region for receiving a write command through a first pad portion to generate a column enable signal used in creation of a column selection signal; a second edge region including a data transmission control circuit capable of receiving an input data and a data strobe signal through a second pad portion and capable of receiving an address signal from the first pad portion to generate and output transmission data, the data transmission control circuit capable of outputting the column enable signal transmitted from the first edge region; and a core region including a column control portion that is capable of processing the transmission data in response to the column enable signal outputted from the second edge region to send the transmission data to bit lines electrically connected to memory cells.

Abstract translation: 一种半导体存储器件，包括：第一边缘区域，用于通过第一焊盘部分接收写入命令，以产生用于创建列选择信号的列使能信号; 第二边缘区域，包括能够通过第二焊盘部分接收输入数据和数据选通信号的数据传输控制电路，并且能够从第一焊盘部分接收地址信号以产生和输出传输数据，数据传输控制电路 能够输出从第一边缘区域发送的列使能信号; 以及核心区域，包括列控制部分，其能够响应于从第二边缘区域输出的列使能信号来处理传输数据，以将传输数据发送到与存储器单元电连接的位线。

公开(公告)号：US20120008452A1

公开(公告)日：2012-01-12

申请号：US13241847

申请日：2011-09-23

Applicant: Kyong Ha LEE

Inventor： Kyong Ha LEE

IPC: G11C8/18

CPC classification number: G11C7/222 ,  G11C7/1027 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C8/04 ,  G11C8/10

Abstract: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.

Abstract translation: 半导体集成电路包括命令解码器，移位寄存器单元和命令地址锁存单元。 命令解码器响应于定义写入和读取模式的外部命令，并且被配置为使用上升或下降时钟根据外部命令提供写入命令或读取命令。 移位寄存器单元被配置为响应写入命令将外部地址和写入命令移位写入延迟。 列地址锁存单元被配置为在读取模式下锁存并提供外部地址作为列地址，并锁存从移位寄存器单元提供的写入地址，并将写入地址作为列地址提供给 写模式。