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    Multichannel Metal Oxide Semiconductor (MOS) Transistors
    1.
    发明申请
    Multichannel Metal Oxide Semiconductor (MOS) Transistors 审中-公开
    多通道金属氧化物半导体（MOS）晶体管

    公开(公告)号：US20100109087A1

    公开(公告)日：2010-05-06

    申请号：US12687613

    申请日：2010-01-14

    申请人： Kyoung-Hwan Yeo ,  Dong-Gun Park ,  Jeong-Dong Choe

    发明人： Kyoung-Hwan Yeo ,  Dong-Gun Park ,  Jeong-Dong Choe

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66484 ,  H01L21/8221 ,  H01L21/823412 ,  H01L27/0688 ,  H01L29/7831

    摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate an a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is positioned between the source region and the drain region. A horizontal channel is provided between the source and drain regions. The horizontal channel includes at least two spaced apart horizontal channel regions. Related methods of fabricating MOS transistors are also provided.

    摘要翻译： 提供金属氧化物半导体（MOS）晶体管的单元电池，其包括集成电路基板和集成电路基板上的MOS晶体管。 MOS晶体管包括源极区，漏极区和栅极。 栅极位于源极区域和漏极区域之间。 在源区和漏区之间提供水平通道。 水平通道包括至少两个间隔开的水平通道区域。 还提供了制造MOS晶体管的相关方法。

    Semiconductor device employing buried insulating layer and method of fabricating the same
    2.
    发明授权
    Semiconductor device employing buried insulating layer and method of fabricating the same 失效
    采用埋层绝缘层的半导体器件及其制造方法

    公开(公告)号：US07575964B2

    公开(公告)日：2009-08-18

    申请号：US11944260

    申请日：2007-11-21

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Kyoung-Hwan Yeo

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Kyoung-Hwan Yeo

    IPC分类号： H01L21/337

    CPC分类号： H01L29/66651 ,  H01L27/10873 ,  H01L29/0653 ,  H01L29/66659

    摘要： A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.

    摘要翻译： 半导体器件采用非对称埋层绝缘层及其制造方法。 半导体器件包括下半导体衬底。 上硅图案位于下半导体衬底上。 上部硅图案包括通道区域以及由沟道区域彼此间隔开的源极区域和漏极区域。 栅电极与上硅图案电绝缘，并且在沟道区域上相交。 位线和单元电容器分别电连接到源极区域和漏极区域。 掩埋绝缘层插入在漏区和下半导体衬底之间。 掩埋绝缘层具有部分插入在沟道区域和下半导体衬底之间的延伸部分。

    Methods of fabricating multichannel metal oxide semiconductor (MOS) transistors
    3.
    发明授权
    Methods of fabricating multichannel metal oxide semiconductor (MOS) transistors 有权
    制造多通道金属氧化物半导体（MOS）晶体管的方法

    公开(公告)号：US07670912B2

    公开(公告)日：2010-03-02

    申请号：US10797463

    申请日：2004-03-10

    申请人： Kyoung-Hwan Yeo ,  Dong-Gun Park ,  Jeong-Dong Choe

    发明人： Kyoung-Hwan Yeo ,  Dong-Gun Park ,  Jeong-Dong Choe

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66484 ,  H01L21/8221 ,  H01L21/823412 ,  H01L27/0688 ,  H01L29/7831

    摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate an a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is positioned between the source region and the drain region. A horizontal channel is provided between the source and drain regions. The horizontal channel includes at least two spaced apart horizontal channel regions. Related methods of fabricating MOS transistors are also provided.

    摘要翻译： 提供金属氧化物半导体（MOS）晶体管的单元电池，其包括集成电路基板和集成电路基板上的MOS晶体管。 MOS晶体管包括源极区，漏极区和栅极。 栅极位于源极区域和漏极区域之间。 在源区和漏区之间提供水平通道。 水平通道包括至少两个间隔开的水平通道区域。 还提供了制造MOS晶体管的相关方法。

    Semiconductor device employing buried insulating layer and method of fabricating the same
    4.
    发明授权
    Semiconductor device employing buried insulating layer and method of fabricating the same 有权
    采用埋层绝缘层的半导体器件及其制造方法

    公开(公告)号：US07321144B2

    公开(公告)日：2008-01-22

    申请号：US11011258

    申请日：2004-12-13

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Kyoung-Hwan Yeo

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Kyoung-Hwan Yeo

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L29/66651 ,  H01L27/10873 ,  H01L29/0653 ,  H01L29/66659

    摘要： A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.

    摘要翻译： 半导体器件采用非对称埋层绝缘层及其制造方法。 半导体器件包括下半导体衬底。 上硅图案位于下半导体衬底上。 上部硅图案包括通道区域以及由沟道区域彼此间隔开的源极区域和漏极区域。 栅电极与上硅图案电绝缘，并且在沟道区域上相交。 位线和单元电容器分别电连接到源极区域和漏极区域。 掩埋绝缘层插入在漏区和下半导体衬底之间。 掩埋绝缘层具有部分插入在沟道区域和下半导体衬底之间的延伸部分。

    Semiconductor device employing buried insulating layer and method of fabricating the same
    5.
    发明申请
    Semiconductor device employing buried insulating layer and method of fabricating the same 有权
    采用埋层绝缘层的半导体器件及其制造方法

    公开(公告)号：US20050133881A1

    公开(公告)日：2005-06-23

    申请号：US11011258

    申请日：2004-12-13

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Kyoung-Hwan Yeo

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Kyoung-Hwan Yeo

    IPC分类号： H01L27/108 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L29/00 ,  H01L29/06

    CPC分类号： H01L29/66651 ,  H01L27/10873 ,  H01L29/0653 ,  H01L29/66659

    摘要： A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.

    摘要翻译： 半导体器件采用非对称埋层绝缘层及其制造方法。 半导体器件包括下半导体衬底。 上硅图案位于下半导体衬底上。 上部硅图案包括通道区域以及由沟道区域彼此间隔开的源极区域和漏极区域。 栅电极与上硅图案电绝缘，并且在沟道区域上相交。 位线和单元电容器分别电连接到源极区域和漏极区域。 掩埋绝缘层插入在漏区和下半导体衬底之间。 掩埋绝缘层具有部分插入在沟道区域和下半导体衬底之间的延伸部分。

    Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) Including Recessed Channel Regions
    6.
    发明申请
    Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) Including Recessed Channel Regions 审中-公开
    金属氧化物半导体场效应晶体管（MOSFET）包括嵌入式通道区域

    公开(公告)号：US20110079831A1

    公开(公告)日：2011-04-07

    申请号：US12966362

    申请日：2010-12-13

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Chang-Sub Lee ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Chang-Sub Lee ,  Jeong-Dong Choe

    IPC分类号： H01L29/772

    CPC分类号： H01L29/66583 ,  H01L29/1037 ,  H01L29/66651

    摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided.

    摘要翻译： 金属氧化物半导体（MOS）晶体管的单位电池在集成电路基板上具有集成电路基板和MOS晶体管。 MOS晶体管包括源极区，漏极区和栅极。 栅极在源极区域和漏极区域之间。 在源区和漏区之间提供沟道区。 沟道区具有比源区和漏区的底表面低的凹陷区域。 还提供了制造晶体管的相关方法。

    Vertical Channel Fin Field-Effect Transistors Having Increased Source/Drain Contact Area and Methods for Fabricating the Same
    7.
    发明申请
    Vertical Channel Fin Field-Effect Transistors Having Increased Source/Drain Contact Area and Methods for Fabricating the Same 有权
    具有增加的源极/漏极接触面积的垂直沟道鳍效应晶体管及其制造方法

    公开(公告)号：US20100044784A1

    公开(公告)日：2010-02-25

    申请号：US12613025

    申请日：2009-11-05

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Dong-Won Kim

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Dong-Won Kim

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/78618

    摘要： A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.

    摘要翻译： 翅片场效应晶体管（FinFET）器件包括其中具有第一和第二源极/漏极区域的鳍状有源区域以及从半导体衬底垂直突出的沟道区域。 栅电极形成在沟道区的上表面和侧壁上。 第一和第二源极/漏极触点形成在栅极电极的相对侧的鳍状有源区域的第一和第二源极/漏极区域的相应上表面和侧壁上。 沟道区域可以比鳍状有源区域的第一和第二源极/漏极区域窄。

    Semiconductor devices having a field effect transistor and methods of fabricating the same
    9.
    发明授权
    Semiconductor devices having a field effect transistor and methods of fabricating the same 有权
    具有场效应晶体管的半导体器件及其制造方法

    公开(公告)号：US07247896B2

    公开(公告)日：2007-07-24

    申请号：US11090740

    申请日：2005-03-24

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Jeong-Dong Choe

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/785 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78687 ,  Y10S438/933

    摘要： A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses over the device active pattern, interposed by a gate insulation layer. A support pattern is preferably interposed between the device active pattern and the substrate. The support pattern can be disposed under the gate electrode. A filling insulation pattern is preferably disposed between the device active pattern and the filling insulation pattern. The filling insulation pattern may be disposed under the source/drain region. A device active pattern under the gate electrode is preferably formed of a strained silicon having a lattice width wider than a silicon lattice.

    摘要翻译： 提供具有场效应晶体管的半导体器件及其形成方法。 半导体器件优选地包括设置在衬底的预定区域上的器件有源图案。 栅电极优选地跨过器件有源图案，由栅极绝缘层插入。 支撑图案优选地插入在器件活性图案和基底之间。 支撑图案可以设置在栅电极下方。 填充绝缘图案优选地设置在装置活性图案和填充绝缘图案之间。 填充绝缘图案可以设置在源极/漏极区域下方。 栅电极下方的器件有源图案优选由具有比硅晶格宽的晶格宽度的应变硅形成。