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公开(公告)号：US5345419A
公开(公告)日：1994-09-06
申请号：US15769
申请日：1993-02-10
摘要： A first in, first out memory (FIFO) includes a multi-port memory array, which is accessed for read/write operations by activating a selected read or write word line. The read word line is controlled by a read shift register, and the write word line is controlled by a write shift register. In order to generate "full" and "empty" flags, the voltage state of read and write word lines are determined in "match circuits", which compare the locations of the read and write pointers. This eliminates the use of counters, and allows the shift registers and word line match circuits to be an integral part of a single-block regular structure. Furthermore, it allows the FIFO to be readily expanded to multiple numbers of words and bits per word.
摘要翻译： 先进先出存储器（FIFO）包括多端口存储器阵列，其通过激活所选择的读取或写入字线来进行读取/写入操作。 读取字线由读取移位寄存器控制，写入字线由写入移位寄存器控制。 为了产生“满”和“空”标志，在“匹配电路”中确定读写字线的电压状态，比较读写指针的位置。 这消除了使用计数器，并允许移位寄存器和字线匹配电路成为单块规则结构的组成部分。 此外，它允许FIFO容易地扩展到单个字的多个字和位。
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公开(公告)号：US07242634B2
公开(公告)日：2007-07-10
申请号：US11290205
申请日：2005-11-30
IPC分类号： G11C8/00
CPC分类号： G11C8/08
摘要： In certain embodiments, the present invention is a word-line driver for an address decoder that decodes a multi-bit address to enable access to a row of circuit elements such as memory cells in a block of memory implemented in a dedicated memory device or as part of a larger device, such as an FPGA. The word-line driver has a feed-back latch for each word-line that ensures that the word-line is not energized when that word-line is not selected for access. By controlling the feed-back latch using a decoded address bit value rather than a pre-charged enable signal as do some prior-art dynamic word-line drivers, the word-line driver prevents undesirable energizing of multiple word-lines. The word-line driver can be implemented using less layout area and less power than some analogous prior-art static word-line drivers.
摘要翻译： 在某些实施例中，本发明是用于地址解码器的字线驱动器，其解码多位地址以使得能够访问电路元件行，例如在专用存储器件中实现的存储器块中的存储器单元，或者如 更大的器件的一部分，如FPGA。 字线驱动器具有用于每个字线的反馈锁存器，以确保当该字线未被选择用于访问时字线不通电。 通过使用解码的地址位值而不是一些现有技术的动态字线驱动器的预充电使能信号控制反馈锁存器，字线驱动器防止多个字线的不期望的通电。 可以使用比一些类似的现有技术的静态字线驱动器更少的布局面积和更少的功率来实现字线驱动器。
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公开(公告)号：US07215149B1
公开(公告)日：2007-05-08
申请号：US11012550
申请日：2004-12-15
IPC分类号： H03K19/0175
CPC分类号： H03K19/00384 , H03K3/356104 , H03K19/018521
摘要： An electrical system has a master circuit and an interface (I/F) circuit. The master circuit generates a master output signal. The I/F circuit receives an I/F input signal and a flag signal and generates an I/F output signal for application to a slave circuit, wherein the I/F input signal is based on the master output signal, and the interface circuit generates the L/F output signal either dependent on or independent of the I/F input signal as indicated by the flag signal.
摘要翻译： 电气系统具有主电路和接口（I / F）电路。 主电路产生主输出信号。 I / F电路接收I / F输入信号和标志信号，并产生用于应用于从电路的I / F输出信号，其中I / F输入信号基于主输出信号，并且接口电路 产生依赖于或独立于I / F输入信号的L / F输出信号，如标志信号所示。
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4.发明授权Programmable logic device having a configurable DRAM with transparent refresh 有权具有可配置DRAM和可透明刷新的可编程逻辑器件公开(公告)号：US07129749B1
公开(公告)日：2006-10-31
申请号：US10974305
申请日：2004-10-27
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/1776 , H03K19/17764 , H03K19/1778
摘要： A programmable logic device (PLD) having a programmable routing structure that employs non-static memory cells, such as dynamic random access memory (DRAM) cells, to control configurable circuit elements, such as pass-transistors and/or MUXes. In a representative embodiment, each DRAM cell is connected to its corresponding configurable circuit element using a buffer adapted to stabilize the output voltage generated by the cell and offset the effect of charge leakage from the cell capacitor. In addition, refresh circuitry associated with the DRAM cell periodically restores the charge in the cell capacitor using a refresh operation that is performed in the background, without disturbing the user functions of the PLD. Advantageously, a relatively large capacitance associated with a DRAM cell makes a PLD of the invention less susceptible to soft errors than a prior-art PLD that relies on SRAM cells for configuration control of its routing structure.
摘要翻译： 具有可编程路由结构的可编程逻辑器件（PLD），其使用诸如动态随机存取存储器（DRAM）单元的非静态存储器单元来控制可配置的电路元件，例如传输晶体管和/或MUX。 在代表性的实施例中，每个DRAM单元使用缓冲器连接到其对应的可配置电路元件，该缓冲器适于稳定由单元产生的输出电压并抵消来自单元电容器的电荷泄漏的影响。 此外，与DRAM单元相关联的刷新电路使用在后台执行的刷新操作来周期性地恢复单元电容器中的电荷，而不会干扰PLD的用户功能。 有利地，与DRAM单元相关联的相对大的电容使得本发明的PLD比依赖于SRAM单元的现有技术的PLD更不易受软错误的影响，用于其路由结构的配置控制。
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5.发明授权Address isolation for user-defined configuration memory in programmable devices 有权可编程器件中用户定义的配置存储器的地址隔离公开(公告)号：US07196963B1
公开(公告)日：2007-03-27
申请号：US11251682
申请日：2005-10-17
CPC分类号： G11C11/412
摘要： In one embodiment of the invention, a block of configuration memory has rows of memory cells, at least one row having a set of one or more dual-port memory cells adapted to selectively store either configuration data or local data. The configuration address line for that row is segmented such that the address line is connected to the configuration address ports of the dual-port memory cells via access control circuitry that can be programmably configured to prevent access to those memory cells via the configuration address line. The access control circuitry enables local data to be efficiently and accurately stored in the dual-port memory cells without interference from configuration readback operations during normal operation or from partial reconfiguration of the configuration memory.
摘要翻译： 在本发明的一个实施例中，一组配置存储器具有一行存储器单元，至少一行具有一组一个或多个双端口存储器单元，其适于选择性地存储配置数据或本地数据。 该行的配置地址线被分段，使得地址线经由访问控制电路连接到双端口存储器单元的配置地址端口，访问控制电路可编程地配置为阻止经由配置地址线访问那些存储器单元。 访问控制电路使得本地数据能够在正常操作期间或者从配置存储器的部分重新配置中有效且准确地存储在双端口存储单元中，而不受配置回读操作的干扰。
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公开(公告)号：US07161862B1
公开(公告)日：2007-01-09
申请号：US10996283
申请日：2004-11-22
申请人： Mou C. Lin , Zheng Chen , Larry R. Fenstermaker
发明人： Mou C. Lin , Zheng Chen , Larry R. Fenstermaker
IPC分类号： G11C7/02
CPC分类号： G11C7/065
摘要： A memory sense amplifier includes an output and a complement output. The sense amplifier is configured such that a memory cell driving the bit line low enables latching of the bit line low by enabling pull-up of the complement output, and the memory cell driving the complement bit line low enables latching of the complement bit line low by enabling pull-up of the output.
摘要翻译： 存储读出放大器包括输出和补码输出。 读出放大器被配置为使得驱动位线低的存储单元通过使补码输出上拉而使位线锁存为低电平，并且驱动补码位线的存储单元为低电平使得能够将补码位线锁存 通过启用输出的上拉。
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公开(公告)号：US07429875B2
公开(公告)日：2008-09-30
申请号：US11638156
申请日：2006-12-13
IPC分类号： H03K19/094
CPC分类号： H03K19/17792 , H03K19/17728
摘要： A logic circuit is disclosed that is tolerant of logic signals with voltages different from the voltage of the logic circuit power supply. In one embodiment, the logic circuit has an inverting amplifier therein, the amplifier having at least one input and an output and is powered by the power supply. A first transistor, in responsive to the output of the amplifier, biases the input of the amplifier to assure substantially no static current flows through the amplifier when a logic-low is present on the amplifier output. A second transistor couples at least one logic input of the logic circuit to the input of the amplifier. In one embodiment, the second transistor impedes static current flow from the first transistor, through the second transistor, to the logic input. Various other embodiments of the logic circuit include a latch/flip-flop, multiplexer, and a complex logic gate.
摘要翻译： 公开了一种逻辑电路，其耐受具有与逻辑电路电源的电压不同的电压的逻辑信号。 在一个实施例中，逻辑电路在其中具有反相放大器，放大器具有至少一个输入和输出，并由电源供电。 响应于放大器的输出的第一晶体管偏置放大器的输入，以确保当放大器输出上存在逻辑低电平时，基本上没有静态电流流过放大器。 第二晶体管将逻辑电路的至少一个逻辑输入耦合到放大器的输入端。 在一个实施例中，第二晶体管阻止从第一晶体管通过第二晶体管到逻辑输入端的静态电流流动。 逻辑电路的各种其它实施例包括锁存/触发器，多路复用器和复合逻辑门。
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公开(公告)号：US07263024B2
公开(公告)日：2007-08-28
申请号：US11252094
申请日：2005-10-17
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/08 , G11C8/18 , G11C11/419
摘要： In one embodiment of the invention, an address decoder for decoding a word-line address to energize a word line in a block of computer memory. Instead of relying on a distinct enable signal, a clock signal provides a reset function and an enable function to the address decoder. In one implementation, the address decoder includes negative-level-sense latches and 3-input AND gates to generate decoded address bits. Using the clock signal as one of the inputs to the AND gates ensures that all of the decoded address bits are 0 when the clock signal is low and that exactly one decoded address bit is 1 when the clock signal is high. In this way, the address decoder ensures that two or more word lines are not energized at the same time.
摘要翻译： 在本发明的一个实施例中，地址解码器用于解码字线地址以激励计算机存储器的块中的字线。 时钟信号不是依赖于明显的使能信号，而是向地址解码器提供复位功能和使能功能。 在一个实现中，地址解码器包括负电平检测锁存器和3输入与门以产生解码的地址位。 使用时钟信号作为与门的输入之一确保当时钟信号为低电平时所有解码的地址位都为0，而当时钟信号为高电平时，所有解码的地址位都为1。 以这种方式，地址解码器确保两个或多个字线不被同时通电。
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公开(公告)号：US06882555B2
公开(公告)日：2005-04-19
申请号：US10464083
申请日：2003-06-18
IPC分类号： G11C7/12 , G11C11/419 , G11C5/06
CPC分类号： G11C7/12 , G11C11/419
摘要： Systems and methods are disclosed for implementing configuration memory on a programmable logic device. For example, in accordance with one embodiment of the present invention, bi-directional buffers are implemented between sections of a column of memory. The buffers may provide buffering for data lines extending through the column of memory.
摘要翻译： 公开了用于在可编程逻辑器件上实现配置存储器的系统和方法。 例如，根据本发明的一个实施例，双向缓冲器在存储器列的部分之间实现。 缓冲器可以为延伸通过存储器列的数据线提供缓冲。
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公开(公告)号：US20080143380A1
公开(公告)日：2008-06-19
申请号：US11638156
申请日：2006-12-13
IPC分类号： H03K19/177
CPC分类号： H03K19/17792 , H03K19/17728
摘要： A logic circuit is disclosed that is tolerant of logic signals with voltages different from the voltage of the logic circuit power supply. In one embodiment, the logic circuit has an inverting amplifier therein, the amplifier having at least one input and an output and is powered by the power supply. A first transistor, in responsive to the output of the amplifier, biases the input of the amplifier to assure substantially no static current flows through the amplifier when a logic-low is present on the amplifier output. A second transistor couples at least one logic input of the logic circuit to the input of the amplifier. In one embodiment, the second transistor impedes static current flow from the first transistor, through the second transistor, to the logic input. Various other embodiments of the logic circuit include a latch/flip-flop, multiplexer, and a complex logic gate.
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