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10 条记录 (耗时 0.017 秒)

    Fifo with word line match circuits for flag generation
    1.
    发明授权
    Fifo with word line match circuits for flag generation 失效
    Fifo与字线匹配电路用于旗帜生成

    公开(公告)号：US5345419A

    公开(公告)日：1994-09-06

    申请号：US15769

    申请日：1993-02-10

    申请人： Larry R. Fenstermaker ,  Kevin J. O'Connor

    发明人： Larry R. Fenstermaker ,  Kevin J. O'Connor

    IPC分类号： G06F5/14 ,  G06F5/10 ,  G11C7/00 ,  G11C8/16 ,  G11C8/00

    CPC分类号： G06F5/14 ,  G11C8/16

    摘要： A first in, first out memory (FIFO) includes a multi-port memory array, which is accessed for read/write operations by activating a selected read or write word line. The read word line is controlled by a read shift register, and the write word line is controlled by a write shift register. In order to generate "full" and "empty" flags, the voltage state of read and write word lines are determined in "match circuits", which compare the locations of the read and write pointers. This eliminates the use of counters, and allows the shift registers and word line match circuits to be an integral part of a single-block regular structure. Furthermore, it allows the FIFO to be readily expanded to multiple numbers of words and bits per word.

    摘要翻译： 先进先出存储器（FIFO）包括多端口存储器阵列，其通过激活所选择的读取或写入字线来进行读取/写入操作。 读取字线由读取移位寄存器控制，写入字线由写入移位寄存器控制。 为了产生“满”和“空”标志，在“匹配电路”中确定读写字线的电压状态，比较读写指针的位置。 这消除了使用计数器，并允许移位寄存器和字线匹配电路成为单块规则结构的组成部分。 此外，它允许FIFO容易地扩展到单个字的多个字和位。

    Field effect transistor inverter-level shifter circuitry
    3.
    发明授权
    Field effect transistor inverter-level shifter circuitry 失效
    场效应晶体管反相器电平移位电路

    公开(公告)号：US4568844A

    公开(公告)日：1986-02-04

    申请号：US467215

    申请日：1983-02-17

    申请人： Kevin J. O'Connor

    发明人： Kevin J. O'Connor

    IPC分类号： H03K5/02 ,  H03K19/0185 ,  H03K19/0944 ,  H03K19/003 ,  H03K17/10 ,  H03K19/094

    CPC分类号： H03K19/09445 ,  H03K19/018507

    摘要： A field effect transistor inverter-level shifter circuit which accepts TTL input level signals and generates MOS output level signals consists of the series combination of a load device, an enhancement mode transistor, and a depletion mode transistor. The gates of the enhancement and depletion mode transistors are connected to an input terminal. The source of the enhancement transistor is connected to the drain of the depletion transistor. The depletion transistor acts to control the potential of the source of the enhancement transistor so as to allow it to tolerate worse case TTL input potential "0" levels while not becoming more than only weakly biased on.

    摘要翻译： 接收TTL输入电平信号并产生MOS输出电平信号的场效应晶体管反相器电平移位器电路由负载器件，增强型晶体管和耗尽型晶体管的串联组合构成。 增强型和耗尽型晶体管的栅极连接到输入端。 增强晶体管的源极连接到耗尽晶体管的漏极。 耗尽晶体管用于控制增强晶体管的源极的电位，以便允许其容忍更差的TTL输入电位“0”电平，同时不会变得仅仅被弱偏置。

    Anti-atherosclerotic diaryl compounds
    4.
    发明授权
    Anti-atherosclerotic diaryl compounds 失效
    抗动脉粥样硬化二芳基化合物

    公开(公告)号：US5395853A

    公开(公告)日：1995-03-07

    申请号：US157685

    申请日：1993-11-24

    申请人： William P. Jackson ,  Clifford J. Harris ,  Richard J. Arrowsmith ,  John G. Dann ,  Kevin J. O'Connor ,  Robert F. G. Booth

    发明人： William P. Jackson ,  Clifford J. Harris ,  Richard J. Arrowsmith ,  John G. Dann ,  Kevin J. O'Connor ,  Robert F. G. Booth

    IPC分类号： C07C233/07 ,  C07C233/11 ,  C07C271/44 ,  C07C275/24 ,  C07C275/28 ,  C07C275/30 ,  C07C279/28 ,  C07C327/44 ,  A61K31/155 ,  A61K31/17 ,  C07C279/18

    CPC分类号： C07C233/07 ,  C07C233/11 ,  C07C271/44 ,  C07C275/24 ,  C07C275/28 ,  C07C275/30 ,  C07C279/28 ,  C07C327/44 ,  C07C2101/14

    摘要： The present invention is concerned with compounds of formula (I) ##STR1## wherein m is 0 or 1;W is hydrogen, a C.sub.1-16 straight, branched, or cyclic alkyl group, or a C.sub.2-16 straight, branched, or cyclic alkenyl or alkynyl group, orPh(CH.sub.2).sub.n -- where Ph is phenyl and n is an integer of from 0 to 2, the phenyl group being optionally substituted by one or more atoms or groups independently selected from halogen, hydroxy, nitro, C.sub.1-4 alkoxy and C.sub.1-4 alkyl wherein one or more of the hydrogen atoms in said alkyl group is optionally replaced by halogen, orR.sup.1 NHCO-- where R.sup.1 is hydrogen or a C.sub.1-6 alkyl group, orR.sup.2 CONH-- where R.sup.2 is hydrogen or a C.sub.1-6 alkyl group; ##STR2## Y is --(CH.sub.2).sub.q, where q is an integer of from 1 to 3, or --CH.dbd.CH-- (E or Z);Z is a C.sub.1-6 alkyl group optionally substituted by one or more independently selected polar groups; andring A is optionally substituted by one or more atoms or groups independently selected from halogen, hydroxy, nitro, C.sub.1-4 alkoxy and C.sub.1-4 alkyl wherein one or more of the hydrogen atoms in said alkyl group is optionally replaced by halogen;provided said compound of formula (I) is not N-{2-[(4-methyl-phenyl)methyl]phenyl}acetamide or .alpha.-(p-tolyl)-o-cresol carbanilate; and salts, solvates and physiologically functional derivatives thereof, processes for the preparation of these compounds, pharmaceutical formulations containing them and their use in medicine.

    摘要翻译： 本发明涉及式（I）的化合物：其中m为0或1; W是氢，C1-16直链，支链或环状烷基或C2-16直链，支链或环状烯基或炔基或Ph（CH2）n-，其中Ph是苯基，n是整数 0至2，苯基任选被一个或多个独立地选自卤素，羟基，硝基，C 1-4烷氧基和C 1-4烷基的一个或多个原子或基团取代，其中所述烷基中的一个或多个氢原子是任选的 被卤素取代，或R1NHCO-，其中R1是氢或C1-6烷基，或R2CONH-，其中R2是氢或C1-6烷基; Y是 - （CH 2）q，其中q是1至3的整数，或-CH = CH-（E或Z）; Z是任选被一个或多个独立选择的极性基团取代的C 1-6烷基; 并且环A任选被一个或多个独立地选自卤素，羟基，硝基，C 1-4烷氧基和C 1-4烷基的原子或基团取代，其中所述烷基中的一个或多个氢原子任选被卤素取代; 所述式（I）化合物不是N- {2 - [（4-甲基 - 苯基）甲基]苯基}乙酰胺或α-（对甲苯基） - 邻甲酚氨基苯甲酸酯; 及其盐，溶剂合物及其生理功能衍生物，制备这些化合物的方法，含有它们的药物制剂及其在药物中的用途。

    Dual port complementary memory
    5.
    发明授权
    Dual port complementary memory 失效
    双口互补存储器

    公开(公告)号：US4660177A

    公开(公告)日：1987-04-21

    申请号：US691418

    申请日：1985-01-14

    申请人： Kevin J. O'Connor

    发明人： Kevin J. O'Connor

    IPC分类号： G11C11/34 ,  G11C8/16 ,  G11C11/41 ,  G11C11/412 ,  G11C13/00

    CPC分类号： G11C11/412 ,  G11C8/16

    摘要： A dual port memory is implemented in complementary (e.g., CMOS) technology so as to allow simultaneous uncontested read operations to the same memory cell. This is achieved by accessing one node of a bistable static cell through a n-channel and a p-channel access transistor. The opposite node is typically left unconnected to external access means. This technique also reduces the area required to implement the memory cell as compared to prior art NMOS techniques. If desired, an arbitration circuit can be included to arbitrate between simultaneous read/read or read/write operations on the same cell from the two ports.

    摘要翻译： 双端口存储器以互补（例如CMOS）技术实现，以便允许对同一存储器单元的同时无竞争的读取操作。 这通过通过n沟道和p沟道存取晶体管访问双稳态静态单元的一个节点来实现。 相对的节点通常与外部访问装置不连接。 与现有技术的NMOS技术相比，该技术还减少了实现存储器单元所需的面积。 如果需要，可以包括仲裁电路以在来自两个端口的同一小区上的同时读/读或读/写操作之间进行仲裁。

    Static bipolar random access memory
    6.
    发明授权
    Static bipolar random access memory 失效
    静态双极性随机存取存储器

    公开(公告)号：US4400712A

    公开(公告)日：1983-08-23

    申请号：US234453

    申请日：1981-02-13

    申请人： Kevin J. O'Connor

    发明人： Kevin J. O'Connor

    IPC分类号： H01L27/102 ,  H01L27/10 ,  G11C11/40

    CPC分类号： H01L27/1025

    摘要： A static bipolar random access memory employs a novel layout for high packing density. Each cell uses a cross-coupled pair of NPN vertical transistors as drivers merged with a pair of PNP lateral transistors as loads, Schottky diode coupling to the input/output lines and Schottky diode clamping of the internal nodes. The PNP transistors are also partially merged between cells to conserve space. OXIL technology is used to achieve high gain vertical transistors and to provide dielectric isolation.

    摘要翻译： 静态双极性随机存取存储器采用新的布局来实现高封装密度。 每个单元使用交叉耦合的一对NPN垂直晶体管作为驱动器与一对PNP横向晶体管合并作为负载，肖特基二极管耦合到输入/输出线和肖特基二极管钳位内部节点。 PNP晶体管也在单元之间部分合并以节省空间。 OXIL技术用于实现高增益垂直晶体管并提供电介质隔离。

    Anti-atherosclerotic diaryl compounds
    7.
    发明授权
    Anti-atherosclerotic diaryl compounds 失效
    抗动脉粥样硬化二芳基化合物

    公开(公告)号：US5290814A

    公开(公告)日：1994-03-01

    申请号：US971252

    申请日：1992-11-05

    申请人： William P. Jackson ,  Clifford J. Harris ,  Richard J. Arrowsmith ,  John G. Dann ,  Kevin J. O'Connor ,  Robert F. G. Booth

    发明人： William P. Jackson ,  Clifford J. Harris ,  Richard J. Arrowsmith ,  John G. Dann ,  Kevin J. O'Connor ,  Robert F. G. Booth

    IPC分类号： C07C233/07 ,  C07C233/11 ,  C07C271/44 ,  C07C275/24 ,  C07C275/28 ,  C07C275/30 ,  C07C279/28 ,  C07C327/44 ,  A61K31/155 ,  A61K31/17 ,  C07C279/18

    CPC分类号： C07C233/07 ,  C07C233/11 ,  C07C271/44 ,  C07C275/24 ,  C07C275/28 ,  C07C275/30 ,  C07C279/28 ,  C07C327/44 ,  C07C2101/14

    摘要： The present invention is concerned with compounds of formula (I) ##STR1## wherein m is 0 or 1;W is hydrogen, a C.sub.1-16 straight, branched, or cyclic alkyl group, or a C.sub.2-16 straight, branched, or cyclic alkenyl or alkynyl group, or Ph(CH.sub.2).sub.n -- where Ph is phenyl and n is an integer of from 0 to 2, the phenyl group being optionally substituted by one or more atoms or groups independently selected from halogen, hydroxy, nitro, C.sub.1-4 alkoxy and C.sub.1-4 alkyl wherein one or more of the hydrogen atoms in said alkyl group is optionally replaced by halogen, or R.sup.1 NHCO-- where R.sup.1 is hydrogen or a C.sub.1-6 alkyl group, or R.sup.2 CONH-- where R.sup.2 is hydrogen or a C.sub.1-6 alkyl group; X is ##STR2## where A is halogen; Y is --(CH.sub.2).sub.q, where q is an integer of from 1 to 3, or --CH.dbd.CH-- (E or Z);Z is a C.sub.1-6 alkyl group optionally substituted by one or more independently selected polar groups; andring A is optionally substituted by one or more atoms or groups independently selected from halogen, hydroxy, nitro, C.sub.1-4 alkoxy and C.sub.1-4 alkyl wherein one or more of the hydrogen atoms in said alkyl group is optionally replaced by halogen.

    摘要翻译： 本发明涉及式（I）的化合物：其中m为0或1; W是氢，C1-16直链，支链或环状烷基或C2-16直链，支链或环状烯基或炔基或Ph（CH2）n-，其中Ph是苯基，n是整数 0至2，苯基任选被一个或多个独立地选自卤素，羟基，硝基，C 1-4烷氧基和C 1-4烷基的一个或多个原子或基团取代，其中所述烷基中的一个或多个氢原子是任选的 被卤素取代，或R1NHCO-，其中R1是氢或C1-6烷基，或R2CONH-，其中R2是氢或C1-6烷基; X是 其中A是卤素; Y是 - （CH 2）q，其中q是1至3的整数，或-CH = CH-（E或Z）; Z是任选被一个或多个独立选择的极性基团取代的C 1-6烷基; 并且环A任选被一个或多个独立地选自卤素，羟基，硝基，C 1-4烷氧基和C 1-4烷基的原子或基团取代，其中所述烷基中的一个或多个氢原子任选被卤素取代。

    Row-address-decoder-driver circuit
    8.
    依法登记的发明
    Row-address-decoder-driver circuit 失效

    公开(公告)号：USH97H

    公开(公告)日：1986-08-05

    申请号：US451786

    申请日：1982-12-21

    申请人： Kevin J. O'Connor

    发明人： Kevin J. O'Connor

    IPC分类号： G11C8/10 ,  H03K19/017 ,  H03K19/0185

    CPC分类号： G11C8/10 ,  H03K19/01714 ,  H03K19/018557

    摘要： A static noninverting driver circuit is used with a standard static address-row-decoder circuit in order to provide capacitance load drive capability and relatively high-speed operation. The driver circuit uses n-channel enhancement and depletion mode field effect transistors and a feedback bootstrap capacitor to achieve low power-high speed operation with a full VDD output high level.

    Semiconductor-integrated-circuit SRAM-cell array with single-ended current-sensing
    10.
    发明授权
    Semiconductor-integrated-circuit SRAM-cell array with single-ended current-sensing 失效
    具有单端电流检测的半导体集成电路SRAM单元阵列

    公开(公告)号：US5541874A

    公开(公告)日：1996-07-30

    申请号：US522796

    申请日：1995-09-01

    申请人： Kevin J. O'Connor

    发明人： Kevin J. O'Connor

    IPC分类号： H01L27/10 ,  G11C8/16 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/40

    CPC分类号： G11C8/16

    摘要： Each memory cell in an SRAM array contains an auxiliary reading transistor connected across one of the transistors in each cell. A row read line controls the ON-OFF condition of this auxiliary reading transistor. In addition, each cell has two access transistors for connecting the cell to complementary column bit lines The ON-OFF condition of both of these access transistors is controlled by a row write line. Each cell has two power nodes, one connected to a power source such as VDD and the other connected to a column detector line that terminates in a current sensor. The state of the memory cell is sensed by this current sensor. In one embodiment, the power line that brings the voltage VDD to the cells is a column line; in another embodiment, it is a row line. Thus there are a total of four column lines and two row lines in the one embodiment, and a total of three column lines and three row lines in the other embodiment.

    摘要翻译： SRAM阵列中的每个存储单元包含连接在每个单元中的一个晶体管的辅助读取晶体管。 行读取行控制辅助读取晶体管的ON-OFF状态。 此外，每个单元具有用于将单元连接到互补列位线的两个存取晶体管。这两个存取晶体管的导通截止状态由行写入线控制。 每个单元具有两个功率节点，一个连接到诸如VDD的电源，另一个连接到端接在电流传感器中的列检测器线。 存储单元的状态由该电流传感器感测。 在一个实施例中，将电压VDD提供给电池的电力线是列线; 在另一个实施例中，它是行线。 因此，在一个实施例中总共有四条列线和两条行线，另一个实施例中共有三条列线和三条行线。