公开(公告)号：US07274060B2

公开(公告)日：2007-09-25

申请号：US11152793

申请日：2005-06-15

申请人： Martin Popp ,  Frank Jakubowski ,  Juergen Holz ,  Lars Heineck

发明人： Martin Popp ,  Frank Jakubowski ,  Juergen Holz ,  Lars Heineck

IPC分类号： H01L21/8244 ,  H01L29/94

CPC分类号： H01L29/945 ,  H01L21/26586 ,  H01L27/0207 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894

摘要： A memory cell array includes memory cells with storage capacitor and an access transistor. The access transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed beneath the bottom side of each word line. In addition, the word lines are disposed above the bit lines.

摘要翻译： 存储单元阵列包括具有存储电容器和存取晶体管的存储单元。 存取晶体管形成在有源区域中。 存储单元阵列还包括沿第一方向定向的位线和朝向第二方向的字线。 有源区域沿第二方向延伸。 晶体管的每个栅电极的底侧设置在每个字线的底侧的下方。 此外，字线设置在位线上方。

公开(公告)号：US20070032033A1

公开(公告)日：2007-02-08

申请号：US11493931

申请日：2006-07-27

申请人： Lars Heineck ,  Martin Popp

发明人： Lars Heineck ,  Martin Popp

IPC分类号： H01L21/20

CPC分类号： H01L27/10867

摘要： A connecting structure connects a storage electrode of a trench capacitor and a selection transistor that are at least partially formed in a semiconductor substrate. The connecting structure includes a portion of an intermediate layer disposed adjacent to a surface of the storage electrode, and an electrically conducting material disposed adjacent to the intermediate layer and electrically connected to a semiconductor substrate surface portion adjacent to the selection transistor, wherein a part of the connecting structure is disposed above the semiconductor substrate surface so as to be adjacent to a horizontal substrate surface portion.

摘要翻译： 连接结构连接沟槽电容器的存储电极和至少部分地形成在半导体衬底中的选择晶体管。 所述连接结构包括邻近所述存储电极的表面设置的中间层的一部分，以及与所述中间层相邻设置并电连接到与所述选择晶体管相邻的半导体衬底表面部分的导电材料，其中， 连接结构设置在半导体衬底表面上方以与水平衬底表面部分相邻。

公开(公告)号：US20070032032A1

公开(公告)日：2007-02-08

申请号：US11356459

申请日：2006-02-17

申请人： Lars Heineck ,  Martin Popp

发明人： Lars Heineck ,  Martin Popp

IPC分类号： H01L21/20

CPC分类号： H01L27/10867

摘要： A method for manufacturing a surface strap connection between a trench capacitor and a selection transistor includes providing a masking material on a surface of a semiconductor substrate in areas where no trench capacitors have been formed. An undoped semiconductor layer having vertical and horizontal areas is applied. An oblique ion implantation is performed such that a vertical area of the semiconductor layer on which the connecting structure is to be formed is not doped. After removal of the undoped portion of the semiconductor layer, the exposed portion of the masking material is laterally etched, one part of the substrate surface is exposed, and the doped part of the semiconductor layer is removed. An electrically conducting connection material is applied so that an electrical contact exists between the exposed portion of the substrate surface and the storage electrode.

摘要翻译： 用于制造沟槽电容器和选择晶体管之间的表面带连接的方法包括在没有形成沟槽电容器的区域中在半导体衬底的表面上提供掩模材料。 施加具有垂直和水平面积的未掺杂的半导体层。 进行倾斜离子注入，使得要在其上形成连接结构的半导体层的垂直面积不被掺杂。 在去除半导体层的未掺杂部分之后，屏蔽材料的暴露部分被横向蚀刻，衬底表面的一部分被暴露，并且去除半导体层的掺杂部分。 施加导电连接材料，使得在基板表面的暴露部分和存储电极之间存在电接触。

公开(公告)号：US08138538B2

公开(公告)日：2012-03-20

申请号：US12249060

申请日：2008-10-10

申请人： Hans-Peter Moll ,  Gouri Sankar Kar ,  Martin Popp ,  Lars Heineck ,  Peter Lahnor ,  Arnd Scholz ,  Stefan Jakschik ,  Wolfgang Roesner ,  Gerhard Enders ,  Werner Graf ,  Peter Baars ,  Klaus Muemmler ,  Bernd Hintze ,  Andrei Josiek

发明人： Hans-Peter Moll ,  Gouri Sankar Kar ,  Martin Popp ,  Lars Heineck ,  Peter Lahnor ,  Arnd Scholz ,  Stefan Jakschik ,  Wolfgang Roesner ,  Gerhard Enders ,  Werner Graf ,  Peter Baars ,  Klaus Muemmler ,  Bernd Hintze ,  Andrei Josiek

IPC分类号： H01L27/108

CPC分类号： H01L27/10891 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

摘要： One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

摘要翻译： 一个实施例涉及形成在半导体主体上的集成电路，其具有在第一和第二晶体管的源/漏区之间的互连。 互连件包括布置在半导体本体表面下方的金属体。 接触元件建立金属体与第一和第二晶体管的源/漏区之间的电接触。 接触元件沿着第一和第二晶体管的源极/漏极区域之间的连接路径延伸。 还公开了其它方法，装置和系统。

公开(公告)号：US20070290249A1

公开(公告)日：2007-12-20

申请号：US11844853

申请日：2007-08-24

申请人： Martin Popp ,  Frank Jakubowski ,  Juergen Holz ,  Lars Heineck

发明人： Martin Popp ,  Frank Jakubowski ,  Juergen Holz ,  Lars Heineck

IPC分类号： H01L29/94

CPC分类号： H01L29/945 ,  H01L21/26586 ,  H01L27/0207 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894

摘要： An integrated circuit includes a memory cell array comprising memory cells with a transistor. The transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed under the bottom side of each word line. In addition, the word lines are disposed over the bit lines.

摘要翻译： 集成电路包括具有晶体管的存储单元的存储单元阵列。 晶体管形成在有源区域中。 存储单元阵列还包括沿第一方向定向的位线和朝向第二方向的字线。 有源区域沿第二方向延伸。 晶体管的每个栅电极的底侧设置在每个字线的底侧的下方。 此外，字线设置在位线之上。

公开(公告)号：US06916721B2

公开(公告)日：2005-07-12

申请号：US10722360

申请日：2003-11-26

申请人： Lars Heineck ,  Stephan Kudelka ,  Jörn Lützen ,  Hans-Peter Moll ,  Martin Popp ,  Till Schlösser ,  Johann Steinmetz

发明人： Lars Heineck ,  Stephan Kudelka ,  Jörn Lützen ,  Hans-Peter Moll ,  Martin Popp ,  Till Schlösser ,  Johann Steinmetz

IPC分类号： H01L21/20 ,  H01L21/334 ,  H01L21/425 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10867 ,  H01L27/10829 ,  H01L29/66181 ,  H01L29/945

摘要： A method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, using a hard mask with a corresponding mask opening.

摘要翻译： 一种在衬底中制造具有绝缘套环的沟槽电容器的方法，其使用具有相应掩模开口的硬掩模经由掩埋触点将其一侧的衬底电连接。

公开(公告)号：US20100090264A1

公开(公告)日：2010-04-15

申请号：US12249060

申请日：2008-10-10

申请人： Hans-Peter Moll ,  Gouri Sankar Kar ,  Martin Popp ,  Lars Heineck ,  Peter Lahnor ,  Arnd Scholz ,  Stefan Jakschik ,  Wolfgang Roesner ,  Gerhard Enders ,  Werner Graf ,  Peter Baars ,  Klaus Muemmler ,  Bernd Hintze ,  Andrei Josiek

发明人： Hans-Peter Moll ,  Gouri Sankar Kar ,  Martin Popp ,  Lars Heineck ,  Peter Lahnor ,  Arnd Scholz ,  Stefan Jakschik ,  Wolfgang Roesner ,  Gerhard Enders ,  Werner Graf ,  Peter Baars ,  Klaus Muemmler ,  Bernd Hintze ,  Andrei Josiek

IPC分类号： H01L27/108 ,  H01L21/02

CPC分类号： H01L27/10891 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

摘要： One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

摘要翻译： 一个实施例涉及形成在半导体主体上的集成电路，其具有在第一和第二晶体管的源/漏区之间的互连。 互连件包括布置在半导体本体表面下方的金属体。 接触元件建立金属体与第一和第二晶体管的源/漏区之间的电接触。 接触元件沿着第一和第二晶体管的源极/漏极区域之间的连接路径延伸。 还公开了其它方法，装置和系统。

公开(公告)号：US07087492B2

公开(公告)日：2006-08-08

申请号：US10812876

申请日：2004-03-31

申请人： Martin Popp ,  Lars Heineck

发明人： Martin Popp ,  Lars Heineck

IPC分类号： H01L21/4282

CPC分类号： H01L27/10873 ,  H01L21/82345 ,  H01L27/1052 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

摘要： A gate electrode layer is doped in a first section of a semiconductor substrate. By means of a patterning, encapsulated gate electrodes emerge from the gate electrode layer, which gate electrodes are arranged in a high packing density in a first section and are assigned to selection transistors of memory cells, and are arranged in a low packing density in a second section and are assigned to transistors of logic circuits. After a processing of the selection transistors, the encapsulated gate electrodes are uncovered in the second section and are subsequently doped in the same way in each case simultaneously with the respectively assigned source/drain regions. Together with a subsequent siliciding of the gate electrodes and of the source/drain regions, the performance of the transistors in the second section is significantly increased with little additional outlay.

摘要翻译： 在半导体衬底的第一部分中掺杂栅极电极层。 通过图案化，封装的栅电极从栅极电极层出现，该栅电极在第一部分中以高堆积密度排列，并被分配给存储单元的选择晶体管，并以低封装密度布置在 第二部分被分配给逻辑电路的晶体管。 在选择晶体管的处理之后，封装的栅极电极在第二部分中未被覆盖，并且随后以相同的方式在分别被分配的源极/漏极区域中同时掺杂。 与随后的栅电极和源极/漏极区的硅化一起，第二部分中的晶体管的性能显着增加，几乎没有额外的费用。

公开(公告)号：US20050026373A1

公开(公告)日：2005-02-03

申请号：US10812876

申请日：2004-03-31

申请人： Martin Popp ,  Lars Heineck

发明人： Martin Popp ,  Lars Heineck

IPC分类号： H01L21/8234 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/336 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/10873 ,  H01L21/82345 ,  H01L27/1052 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

摘要： A gate electrode layer is doped in a first section of a semiconductor substrate. By means of a patterning, encapsulated gate electrodes emerge from the gate electrode layer, which gate electrodes are arranged in a high packing density in a first section and are assigned to selection transistors of memory cells, and are arranged in a low packing density in a second section and are assigned to transistors of logic circuits. After a processing of the selection transistors, the encapsulated gate electrodes are uncovered in the second section and are subsequently doped in the same way in each case simultaneosly with the respectively assigned source/drain regions. Together with a subsequent siliciding of the gate electrodes and of the source/drain regions, the performance of the transistors in the second section is significantly increased with little additional outlay.

摘要翻译： 在半导体衬底的第一部分中掺杂栅极电极层。 通过图案化，封装的栅电极从栅极电极层出现，该栅电极在第一部分中以高堆积密度排列，并被分配给存储单元的选择晶体管，并以低封装密度布置在 第二部分被分配给逻辑电路的晶体管。 在选择晶体管的处理之后，封装的栅电极在第二部分中未被覆盖，并且随后以与分配的源极/漏极区域同时地以相同的方式被掺杂。 与随后的栅电极和源极/漏极区的硅化一起，第二部分中的晶体管的性能显着增加，几乎没有额外的费用。

公开(公告)号：US20090302380A1

公开(公告)日：2009-12-10

申请号：US12134740

申请日：2008-06-06

申请人： Werner Graf ,  Lars Heineck ,  Martin Popp

发明人： Werner Graf ,  Lars Heineck ,  Martin Popp

IPC分类号： H01L27/105 ,  H01L21/762

CPC分类号： H01L21/76232 ,  H01L21/743 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891

摘要： In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line.

摘要翻译： 在一个实施例中，存储单元包括布置在半导体衬底中的位线和布置在位线附近的位线接触区域。 在形成在半导体衬底中的沟槽中的位线接触区域上方布置字线。 大致U形绝缘层布置在沟槽的底部区域中，并将位线和位线接触区域与字线分离。