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    Method to generate porous organic dielectric
    2.
    发明授权
    Method to generate porous organic dielectric 失效
    生成多孔有机电介质的方法

    公开(公告)号：US07101784B2

    公开(公告)日：2006-09-05

    申请号：US11125549

    申请日：2005-05-10

    申请人： Lawrence A. Clevenger ,  Stephen E. Greco ,  Keith T. Kwietniak ,  Soon-Cheon Seo ,  Chih-Chao Yang ,  Yun-Yu Wang ,  Kwong H. Wong

    发明人： Lawrence A. Clevenger ,  Stephen E. Greco ,  Keith T. Kwietniak ,  Soon-Cheon Seo ,  Chih-Chao Yang ,  Yun-Yu Wang ,  Kwong H. Wong

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76856 ,  H01L2221/1036

    摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).

    摘要翻译： 本发明提供一种形成集成电路结构中的布线层的方法，该集成电路结构形成有机绝缘体，图案化绝缘体，将衬垫沉积在绝缘体上，并将该结构暴露于等离子体，以在绝缘体旁边的区域中形成孔 衬垫。 衬垫形成得足够薄以允许等离子体穿过衬垫并在绝缘体中形成孔。 在等离子体处理期间，等离子体通过衬垫而不影响衬垫。 在等离子体处理之后，可以沉积另外的衬里材料。 此后，导体被沉积，导体的多余部分从结构中移除，使得导体仅保留在绝缘体的图案化部分内。 该方法产生集成电路结构，其具有具有图案化特征的有机绝缘体，衬里图案化特征的衬垫和填充图案化特征的导体。 绝缘体包括与绝缘体的表面区域相接触的孔，该孔与衬垫接触，并且孔仅沿着与衬垫接触的表面区域（衬里不在孔内）存在。

    IC having viabar interconnection and related method
    3.
    发明授权
    IC having viabar interconnection and related method 有权
    IC具有viabar互连及相关方法

    公开(公告)号：US08492268B2

    公开(公告)日：2013-07-23

    申请号：US13410466

    申请日：2012-03-02

    申请人： Dureseti Chidambarrao ,  Stephen E. Greco ,  Kia S. Low

    发明人： Dureseti Chidambarrao ,  Stephen E. Greco ,  Kia S. Low

    IPC分类号： H01L23/52

    CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

    摘要： An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.

    摘要翻译： 一种IC，包括具有在第一方向上延伸的布线的第一金属层; 具有沿与第一方向垂直的第二方向延伸的布线的第二金属层; 以及在所述第一金属层和所述第二金属层之间的第一通孔层，所述第一通孔层包括在所述第一金属层与所述第二金属层垂直重合的第一位置处将所述第一金属层与所述第二金属层互连的viabar， 在第二位置处连接到第一金属层的布线而不是第二金属层的布线。

    IC HAVING VIABAR INTERCONNECTION AND RELATED METHOD
    5.
    发明申请
    IC HAVING VIABAR INTERCONNECTION AND RELATED METHOD 有权
    具有VIABAR互连的IC和相关方法

    公开(公告)号：US20120164758A1

    公开(公告)日：2012-06-28

    申请号：US13410466

    申请日：2012-03-02

    申请人： Dureseti Chidambarrao ,  Stephen E. Greco ,  Kia S. Low

    发明人： Dureseti Chidambarrao ,  Stephen E. Greco ,  Kia S. Low

    IPC分类号： H01L21/66

    CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

    摘要： An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.

    摘要翻译： 一种IC，包括具有在第一方向上延伸的布线的第一金属层; 具有沿与第一方向垂直的第二方向延伸的布线的第二金属层; 以及在所述第一金属层和所述第二金属层之间的第一通孔层，所述第一通孔层包括在所述第一金属层与所述第二金属层垂直重合的第一位置处将所述第一金属层与所述第二金属层互连的viabar， 在第二位置处连接到第一金属层的布线而不是第二金属层的布线。

    Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via
    6.
    发明授权
    Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via 失效
    使用垂直向上延伸的虚拟通孔增加IC中的电迁移寿命和电流密度

    公开(公告)号：US07439173B2

    公开(公告)日：2008-10-21

    申请号：US11869044

    申请日：2007-10-09

    申请人： Stephen E. Greco ,  Chao-Kun Hu ,  Paul S. McLaughlin

    发明人： Stephen E. Greco ,  Chao-Kun Hu ,  Paul S. McLaughlin

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.

    摘要翻译： 公开了一种具有增加的电迁移寿命和允许电流密度的集成电路及其形成方法。 在一个实施例中，集成电路包括连接到至少一个功能通孔的导线，以及至少一个虚拟通孔，其具有与导电线电连接的第一下端，以及电连接（隔离）至任何导电 线。 每个虚拟通孔从导电线垂直向上延伸，并且去除快速扩散路径的一部分，即金属到电介质盖界面，其被金属对金属衬垫界面代替。 因此，每个虚拟通孔可以减少金属扩散速率，从而增加电迁移寿命并允许增加电流密度。

    Interim oxidation of silsesquioxane dielectric for dual damascene process
    7.
    发明授权
    Interim oxidation of silsesquioxane dielectric for dual damascene process 有权
    双重镶嵌工艺的倍半硅氧烷电介质的中间氧化

    公开(公告)号：US06479884B2

    公开(公告)日：2002-11-12

    申请号：US09893786

    申请日：2001-06-29

    申请人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

    发明人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

    IPC分类号： H01L2358

    CPC分类号： H01L21/76808 ,  H01L2221/1063

    摘要： Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

    摘要翻译： 抗蚀剂显影剂可以攻击一些先进的介电材料，例如可以用作集成电路芯片的表面和形成在介电材料表面上的布线层之间的绝缘体的倍半硅氧烷材料。 通过进行抗蚀剂剥离或蚀刻工艺，其中将反应物材料从电介质材料外部供应或释放出来，可以形成非常薄的中间材料的表面保护覆盖层，其不能抵抗显影剂或多种其它材料 这可能会损坏可流动的氧化物材料。 因此，与芯片形成牢固的连接和通孔的双镶嵌工艺可以与具有特别低介电常数的先进电介质相兼容，以最小化导体电容并支持快速的信号传播和抗噪声性，即使导体彼此间隔紧密。

    IC having viabar interconnection and related method
    9.
    发明授权
    IC having viabar interconnection and related method 有权
    IC具有viabar互连及相关方法

    公开(公告)号：US08299622B2

    公开(公告)日：2012-10-30

    申请号：US12186061

    申请日：2008-08-05

    申请人： Dureseti Chidambarrao ,  Stephen E. Greco ,  Kia S. Low

    发明人： Dureseti Chidambarrao ,  Stephen E. Greco ,  Kia S. Low

    IPC分类号： H01L23/52

    CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

    摘要： An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.

    摘要翻译： 一种IC，包括具有在第一方向上延伸的布线的第一金属层; 具有沿与第一方向垂直的第二方向延伸的布线的第二金属层; 以及在所述第一金属层和所述第二金属层之间的第一通孔层，所述第一通孔层包括在所述第一金属层与所述第二金属层垂直重合的第一位置处将所述第一金属层与所述第二金属层互连的viabar， 在第二位置处连接到第一金属层的布线而不是第二金属层的布线。