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    CELL ARCHITECTURE AND METHOD
    1.
    发明申请
    CELL ARCHITECTURE AND METHOD 有权
    细胞结构和方法

    公开(公告)号：US20120331426A1

    公开(公告)日：2012-12-27

    申请号：US13207506

    申请日：2011-08-11

    申请人： Lee-Chung LU ,  Li-Chun TIEN ,  Shyue-Shyh LIN ,  Zhe-Wei JIANG

    发明人： Lee-Chung LU ,  Li-Chun TIEN ,  Shyue-Shyh LIN ,  Zhe-Wei JIANG

    IPC分类号： G06F17/50

    CPC分类号： G03F1/70 ,  G06F17/504 ,  G06F17/5072 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method includes selecting a cell stored in a non-transient computer readable storage medium, arranging a plurality of the cells on a model of a semiconductor device, and creating a mask for the semiconductor device based on the model of the semiconductor device. The cell is designed according to a design rule in which a first power-supply-connection via satisfies a criterion from the group consisting of: i) the first power-supply-connection via is spaced apart from a second power-supply-connection via by a distance that is greater than a threshold distance such that the cell can be fabricated by a single-photolithography single-etch process, or ii) the first power-supply-connection via is coupled to first and second substantially parallel conductive lines that extend along directly adjacent tracks.

    摘要翻译： 一种方法包括：选择存储在非瞬态计算机可读存储介质中的单元，将多个单元布置在半导体器件的模型上，以及基于半导体器件的模型为半导体器件创建掩模。 电池根据设计规则设计，其中第一电源连接通孔满足以下组的标准：i）第一电源连接通孔与第二电源连接通路间隔开 距离大于阈值距离，使得可以通过单光刻单蚀刻工艺制造单元，或者ii）第一电源连接通孔耦合到第一和第二基本平行的导线，其延伸 沿着直接相邻的轨道。

    SYSTEMS AND METHODS OF DESIGNING INTEGRATED CIRCUITS
    3.
    发明申请
    SYSTEMS AND METHODS OF DESIGNING INTEGRATED CIRCUITS 有权
    设计集成电路的系统与方法

    公开(公告)号：US20120240088A1

    公开(公告)日：2012-09-20

    申请号：US13047419

    申请日：2011-03-14

    申请人： Ta-Pen GUO ,  Li-Chun TIEN ,  Shyue-Shyh LIN ,  Mei-Hui HUANG

    发明人： Ta-Pen GUO ,  Li-Chun TIEN ,  Shyue-Shyh LIN ,  Mei-Hui HUANG

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/505 ,  G06F2217/72

    摘要： A method of designing an integrated circuit includes defining at least one dummy layer covering at least one of a portion of a first metallic layer and a portion of a second metallic layer of an integrated circuit. The second metallic layer is disposed over the first metallic layer. The first metallic layer, the second metallic layer and a gate electrode of the integrated circuit have a same routing direction. A logical operation is performed to a file corresponding to the at least one of the portion of the first metallic layer and the portion of the second metallic layer covered by the dummy layer so as to size at least one of the portion of the first metallic layer and the portion of the second metallic layer.

    摘要翻译： 设计集成电路的方法包括限定覆盖第一金属层的一部分和集成电路的第二金属层的一部分中的至少一个的至少一个虚设层。 第二金属层设置在第一金属层上。 集成电路的第一金属层，第二金属层和栅电极具有相同的布线方向。 对与第一金属层的部分的至少一个和由虚设层覆盖的第二金属层的部分相对应的文件执行逻辑操作，以便使第一金属层的至少一个部分 和第二金属层的部分。

    INTERCONNECT STRUCTURE HAVING SMALLER TRANSITION LAYER VIA
    4.
    发明申请
    INTERCONNECT STRUCTURE HAVING SMALLER TRANSITION LAYER VIA 有权
    具有小型过渡层的互连结构

    公开(公告)号：US20130256902A1

    公开(公告)日：2013-10-03

    申请号：US13438565

    申请日：2012-04-03

    申请人： Lee-Chung LU ,  Wen-Hao CHEN ,  Yuan-Te HOU ,  Fang-Yu FAN ,  Yu-Hsiang KAO ,  Dian-Hau CHEN ,  Shyue-Shyh LIN ,  Chii-Ping CHEN

    发明人： Lee-Chung LU ,  Wen-Hao CHEN ,  Yuan-Te HOU ,  Fang-Yu FAN ,  Yu-Hsiang KAO ,  Dian-Hau CHEN ,  Shyue-Shyh LIN ,  Chii-Ping CHEN

    IPC分类号： H01L23/48

    CPC分类号： H01L23/5226 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.

    摘要翻译： 一种互连结构，其包括在衬底上的底层，其中底层包括至少一个底层线和至少一个底层通孔。 互连结构还包括在底层上的过渡层，其中过渡层包括至少一个过渡层线和至少一个过渡层通孔。 互连结构还包括过渡层上的顶层，其中顶层包括至少一个顶层线和至少一个顶层通孔。 所述至少一个过渡层通孔具有比所述至少一个顶层通孔的横截面面积小至少30％的横截面面积。

    METHOD OF MAKING A FINFET, AND FINFET FORMED BY THE METHOD
    5.
    发明申请
    METHOD OF MAKING A FINFET, AND FINFET FORMED BY THE METHOD 有权
    制造FINFET的方法和由该方法形成的FINFET

    公开(公告)号：US20110227162A1

    公开(公告)日：2011-09-22

    申请号：US12725554

    申请日：2010-03-17

    申请人： Chia-Pin LIN ,  Chien-Tai CHAN ,  Hsien-Chin LIN ,  Shyue-Shyh LIN

    发明人： Chia-Pin LIN ,  Chien-Tai CHAN ,  Hsien-Chin LIN ,  Shyue-Shyh LIN

    IPC分类号： H01L27/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

    CPC分类号： H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

    摘要： A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.

    摘要翻译： 一种方法包括形成在半导体衬底之上延伸的finFET的第一和第二鳍片，其间具有浅沟槽隔离（STI）区域，以及STI区域的顶表面与第一鳍片和第二鳍片的顶表面之间的距离。 第一和第二鳍片延伸部分设置在STI区域顶表面上方的第一和第二鳍片的顶表面和侧表面上。 从STI区域去除材料，以增加STI区域的顶表面与第一和第二鳍片的顶表面之间的距离。 保形应力源电介质材料沉积在鳍片和STI区域上。 共形介电应力材料被回流，以流入STI区域的顶表面之上的第一和第二鳍片之间的空间，以向finFET的沟道施加应力。

    INTEGRATED METHOD FOR FORMING HIGH-K METAL GATE FINFET DEVICES
    8.
    发明申请
    INTEGRATED METHOD FOR FORMING HIGH-K METAL GATE FINFET DEVICES 有权
    用于形成高K金属栅极FinFET器件的集成方法

    公开(公告)号：US20110207279A1

    公开(公告)日：2011-08-25

    申请号：US12712594

    申请日：2010-02-25

    申请人： Chia-Pin LIN ,  Wen-Sheh HUANG ,  Tian-Choy GAN ,  Chia-Lung HUNG ,  Hsien-Chin LIN ,  Shyue-Shyh LIN

    发明人： Chia-Pin LIN ,  Wen-Sheh HUANG ,  Tian-Choy GAN ,  Chia-Lung HUNG ,  Hsien-Chin LIN ,  Shyue-Shyh LIN

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66795 ,  H01L29/66803

    摘要： Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations such as an LDD or a PKT implant, are carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx with a low wet etch rate in H3PO4 and dilute HF acid. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.

    摘要翻译： 提供了形成在半导体鳍上的高k金属栅极结构。 在栅极结构和半导体鳍片上形成氮化物层，使用两个单独的沉积操作，首先形成非常薄的氮化物膜。 在两个氮化物膜沉积操作之间进行诸如LDD或PKT注入的植入操作。 第一氮化物膜可以是SiNx或SiCNx，并且第二氮化物膜是SiCNx，在H 3 PO 4中具有低湿蚀刻速率和稀释的HF酸。 可以将氮化物膜组合以形成低湿蚀刻速率间隔物，使得能够进行进一步的处理操作而不损坏下面的结构，而不需要形成另外的虚设间隔物。 进一步的处理操作包括外延硅/ SiGe处理序列和用低蚀刻速率间隔物完整地进行的源极/漏极注入操作。