公开(公告)号：US20130256902A1

公开(公告)日：2013-10-03

申请号：US13438565

申请日：2012-04-03

申请人： Lee-Chung LU ,  Wen-Hao CHEN ,  Yuan-Te HOU ,  Fang-Yu FAN ,  Yu-Hsiang KAO ,  Dian-Hau CHEN ,  Shyue-Shyh LIN ,  Chii-Ping CHEN

发明人： Lee-Chung LU ,  Wen-Hao CHEN ,  Yuan-Te HOU ,  Fang-Yu FAN ,  Yu-Hsiang KAO ,  Dian-Hau CHEN ,  Shyue-Shyh LIN ,  Chii-Ping CHEN

IPC分类号： H01L23/48

CPC分类号： H01L23/5226 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.

摘要翻译： 一种互连结构，其包括在衬底上的底层，其中底层包括至少一个底层线和至少一个底层通孔。 互连结构还包括在底层上的过渡层，其中过渡层包括至少一个过渡层线和至少一个过渡层通孔。 互连结构还包括过渡层上的顶层，其中顶层包括至少一个顶层线和至少一个顶层通孔。 所述至少一个过渡层通孔具有比所述至少一个顶层通孔的横截面面积小至少30％的横截面面积。

公开(公告)号：US20120025273A1

公开(公告)日：2012-02-02

申请号：US12845162

申请日：2010-07-28

申请人： Lee-Chung LU ,  Wen-Hao CHEN ,  Yuan-Te HOU ,  Shen-Feng CHEN ,  Meng-Fu YOU

发明人： Lee-Chung LU ,  Wen-Hao CHEN ,  Yuan-Te HOU ,  Shen-Feng CHEN ,  Meng-Fu YOU

IPC分类号： H01L27/10 ,  G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5036 ,  G06F17/5045 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/82 ,  H01L23/5286 ,  H01L27/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.

摘要翻译： 标准单元半导体集成电路器件设计提供了标准单元半导体器件，其包括消耗更多功率的第一标准单元和用户定义的目标标准单元，或者包括与第一标准单元的操作特性不同的其他操作特性。 使用一个电源轨将标准电池单元路由到地线和电源线，并且使用第一电源轨和第二电源轨将目标电池路由到地线和电源线，以减轻任一电力轨道中的电迁移。 两个电源轨包括上电源轨和下电源轨。 中间导电层可以设置在上部和下部电源轨之间，以通过电池之间的横向互连提供信号路由。

公开(公告)号：US20110291200A1

公开(公告)日：2011-12-01

申请号：US13086186

申请日：2011-04-13

申请人： Ali KESHAVARZI ,  Ta-Pen GUO ,  Helen Shu-Hui CHANG ,  Hsiang-Jen TSENG ,  Shyue-Shyh LIN ,  Lee-Chung LU ,  Chung-Cheng WU ,  Li-Chun TIEN ,  Jung-Chan YANG ,  Shu-Min CHEN ,  Min CAO ,  Yung-Chin HOU

发明人： Ali KESHAVARZI ,  Ta-Pen GUO ,  Helen Shu-Hui CHANG ,  Hsiang-Jen TSENG ,  Shyue-Shyh LIN ,  Lee-Chung LU ,  Chung-Cheng WU ,  Li-Chun TIEN ,  Jung-Chan YANG ,  Shu-Min CHEN ,  Min CAO ,  Yung-Chin HOU

IPC分类号： H01L27/092

CPC分类号： H01L27/092 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/4238 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

摘要翻译： 集成电路包括用于第一类型晶体管的第一扩散区域。 第一类型晶体管包括第一漏极区域和第一源极区域。 用于第二类型晶体管的第二扩散区域与第一扩散区域分离。 第二类型晶体管包括第二漏极区域和第二源极区域。 栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。 第一金属结构与第一源区电耦合。 第二金属结构与第二漏区电耦合。 第三金属结构设置在第一和第二金属结构之上并与第一和第二金属结构电耦合。 第一金属结构体的宽度基本上等于或大于第三金属结构体的宽度。

公开(公告)号：US20120331426A1

公开(公告)日：2012-12-27

申请号：US13207506

申请日：2011-08-11

申请人： Lee-Chung LU ,  Li-Chun TIEN ,  Shyue-Shyh LIN ,  Zhe-Wei JIANG

发明人： Lee-Chung LU ,  Li-Chun TIEN ,  Shyue-Shyh LIN ,  Zhe-Wei JIANG

IPC分类号： G06F17/50

CPC分类号： G03F1/70 ,  G06F17/504 ,  G06F17/5072 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes selecting a cell stored in a non-transient computer readable storage medium, arranging a plurality of the cells on a model of a semiconductor device, and creating a mask for the semiconductor device based on the model of the semiconductor device. The cell is designed according to a design rule in which a first power-supply-connection via satisfies a criterion from the group consisting of: i) the first power-supply-connection via is spaced apart from a second power-supply-connection via by a distance that is greater than a threshold distance such that the cell can be fabricated by a single-photolithography single-etch process, or ii) the first power-supply-connection via is coupled to first and second substantially parallel conductive lines that extend along directly adjacent tracks.

摘要翻译： 一种方法包括：选择存储在非瞬态计算机可读存储介质中的单元，将多个单元布置在半导体器件的模型上，以及基于半导体器件的模型为半导体器件创建掩模。 电池根据设计规则设计，其中第一电源连接通孔满足以下组的标准：i）第一电源连接通孔与第二电源连接通路间隔开 距离大于阈值距离，使得可以通过单光刻单蚀刻工艺制造单元，或者ii）第一电源连接通孔耦合到第一和第二基本平行的导线，其延伸 沿着直接相邻的轨道。

公开(公告)号：US20120210279A1

公开(公告)日：2012-08-16

申请号：US13027520

申请日：2011-02-15

申请人： Chin-Chang HSU ,  Wen-Ju YANG ,  Hsiao-Shu CHAO ,  Yi-Kan CHENG ,  Lee-Chung LU

发明人： Chin-Chang HSU ,  Wen-Ju YANG ,  Hsiao-Shu CHAO ,  Yi-Kan CHENG ,  Lee-Chung LU

IPC分类号： G06F17/50

CPC分类号： G03F1/70 ,  G03F7/70433 ,  G03F7/70466

摘要： Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features.

摘要翻译： 提供了一种用于评估半导体器件级的设计布局并通过分解设计布局来确定和指定由不同光掩模形成的设计布局的不同特征的系统和方法。 这些特征由标记指定，该标记将各种器件特征与将在其上形成的多个光掩模相关联，然后使用双重图案化光刻DPL技术在半导体器件层面上产生。 标记是在设备级完成的，并被包括在由设计公司提供给光掩模铸造厂的电子文件中。 除了正在分解的设计布局的重叠和关键维度考虑之外，在确定和标记各种设备时，还考虑了各种其他设备标准，设计标准处理标准及其相关性以及设备环境和其他设备层 特征。

公开(公告)号：US20120131523A1

公开(公告)日：2012-05-24

申请号：US12950371

申请日：2010-11-19

申请人： Lee-Chung LU ,  Yun-Han LEE ,  Wei-Li CHEN ,  Tan-Li CHOU ,  Kheng-Guan TAN ,  Shi-Hung WANG

发明人： Lee-Chung LU ,  Yun-Han LEE ,  Wei-Li CHEN ,  Tan-Li CHOU ,  Kheng-Guan TAN ,  Shi-Hung WANG

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F2217/02 ,  G06F2217/66

摘要： The present application discloses a method of generating an intellectual property (IP) block design kit including an IP block circuit design and a system-level characteristics table for manufacturing an integrated circuit. According at least one embodiment, the IP block circuit design is generated. The IP block circuit design is simulated based on predetermined configuration sets, and each configuration set has manufacturing options and/or operating conditions. A plurality of system-level models for the predetermined configuration sets are generated based on the simulation of the IP block circuit design. The system-level characteristics table is generated by arranging the predetermined configuration sets and the system-level models in compliance with a system-level characteristics table template of a system-level characteristics modeling device. Then the IP block circuit design and the system-level characteristics table are stored as the IP block design kit.

摘要翻译： 本申请公开了一种生成包括IP块电路设计和用于制造集成电路的系统级特性表的知识产权（IP）块设计套件的方法。 根据至少一个实施例，产生IP块电路设计。 IP块电路设计基于预定的配置集进行仿真，每个配置集都具有制造选项和/或操作条件。 基于IP块电​​路设计的仿真，生成用于预定配置集的多个系统级模型。 通过根据系统级特征建模设备的系统级特征表模板布置预定配置集和系统级模型来生成系统级特征表。 然后将IP块电路设计和系统级特性表存储为IP块设计工具包。

公开(公告)号：US20130087932A1

公开(公告)日：2013-04-11

申请号：US13267310

申请日：2011-10-06

申请人： Lee-Chung LU ,  Li-Chun TIEN ,  Hui-Zhong ZHUANG ,  Mei-Hui HUANG

发明人： Lee-Chung LU ,  Li-Chun TIEN ,  Hui-Zhong ZHUANG ,  Mei-Hui HUANG

IPC分类号： H01L29/41 ,  G06F17/50

CPC分类号： H01L27/0207 ,  G06F17/5068 ,  G06F17/5077 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11885

摘要： A method of designing an integrated circuit includes deploying an active area in a first standard cell. At least one gate electrode is routed, overlapping the active area in the first standard cell. At least one metallic line structure is routed, overlapping the active area in the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. A first power rail is routed substantially orthogonal to the at least one metallic line structure in the first standard cell. The first power rail overlaps the at least one metallic line structure. The first power rail has a flat edge that is adjacent to the at least one metallic line structure. A first connection plug is deployed at a region where the first power rail overlaps the at least one metallic line structure in the first standard cell.

摘要翻译： 设计集成电路的方法包括在第一标准单元中部署有效区域。 至少一个栅电极被路由，与第一标准单元中的有效区重叠。 至少一个金属线结构被路由，与第一标准单元中的有效区重叠。 至少一个金属线结构基本上平行于栅电极。 第一电源轨道基本上正交于第一标准单元中的至少一个金属线结构。 第一电力轨与至少一个金属线结构重叠。 第一动力轨具有与至少一个金属线结构相邻的平坦边缘。 第一连接插头部署在第一电力轨道与第一标准单元中的至少一个金属线结构重叠的区域处。

公开(公告)号：US20110296360A1

公开(公告)日：2011-12-01

申请号：US12788789

申请日：2010-05-27

申请人： Dio WANG ,  Ken-Hsien HSIEH ,  Huang-Yu CHEN ,  Li-Chun TIEN ,  Ru-Gun LIU ,  Lee-Chung LU

发明人： Dio WANG ,  Ken-Hsien HSIEH ,  Huang-Yu CHEN ,  Li-Chun TIEN ,  Ru-Gun LIU ,  Lee-Chung LU

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/00 ,  G06F17/5077 ,  G06F2217/12 ,  G21K5/00

摘要： A method and system checks a double patterning layout and outputs a representation of G0-rule violations and critical G0-spaces. The method includes receiving layout data having patterns, determining whether each distance between adjacent pattern elements is a G0-space, find all G0-space forming a G0-rule violation, finding all G0-space that are critical G0-spaces, and outputting a representation of G0-rule violations and critical G0-spaces to an output device. By resolving G0-rule violations and critical G0-spaces, a design checker can effectively generate a double patterning technology (DPT) compliant layout.

摘要翻译： 一种方法和系统检查双重图案化布局，并输出G0规则违规和关键G0空格的表示。 该方法包括接收具有图案的布局数据，确定相邻图案元素之间的每个距离是否是G0空间，找到形成G0规则违例的所有G0空间，找到作为关键G0空间的所有G0空间，并输出 将G0规则违规和关键G0空格表示为输出设备。 通过解决G0规则违规和关键G0空间，设计检查器可以有效地生成符合双图案技术（DPT）的布局。