公开(公告)号：US08304840B2

公开(公告)日：2012-11-06

申请号：US12846261

申请日：2010-07-29

申请人： Lee-Wee Teo ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

发明人： Lee-Wee Teo ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/02 ,  H01L21/70 ,  H01L27/088

CPC分类号： H01L29/401 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088

摘要： The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width.

摘要翻译： 本公开涉及半导体器件的间隔结构。 半导体器件的示例性结构包括具有第一有源区和第二有源区的衬底; 多个在所述第一有源区上具有栅间距的第一栅电极，其中每个第一栅电极具有第一宽度; 与所述多个第一栅电极相邻的多个第一间隔件，其中每个第一间隔件具有第三宽度; 多个第二栅电极，其具有与第二有源区上的多个第一栅电极相同的栅极间距，其中每个第二栅电极具有大于第一宽度的第二宽度; 以及与所述多个第二栅电极相邻的多个第二间隔件，其中每个第二间隔件具有小于所述第三宽度的第四宽度。

公开(公告)号：US08378428B2

公开(公告)日：2013-02-19

申请号：US12893338

申请日：2010-09-29

申请人： Han-Guan Chew ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

发明人： Han-Guan Chew ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/02

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/82385 ,  H01L29/66545

摘要： The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ⅔ of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ⅓ of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region.

摘要翻译： 应用公开了一种半导体器件，其包括具有第一有源区，第二有源区和具有介于第一和第二有源区之间的第一宽度的隔离区的衬底; 在所述第一有源区上方的P金属栅电极，并且延伸至所述隔离区的第一宽度的至少;; 以及在第二有源区上方的N极金属栅电极，并延伸超过第一宽度的1/3。 N型金属栅电极在隔离区域上电连接到P金属栅电极。

公开(公告)号：US08563389B2

公开(公告)日：2013-10-22

申请号：US13110693

申请日：2011-05-18

申请人： Harry-Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo ,  Bao-Ru Young

发明人： Harry-Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo ,  Bao-Ru Young

IPC分类号： H01L21/20

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0802

摘要： An embodiment of the disclosure includes a method of forming an integrated circuit. A substrate having an active region and a passive region is provided. A plurality of trenches is formed in the passive region. A root mean square of a length and a width of each trench is less than 5 μm. An isolation material is deposited over the substrate to fill the plurality of trenches. The isolation material is planarized to form a plurality of isolation structures. A plurality of silicon gate stacks and at least one silicon resistor stack are formed on the substrate in the active region and on the plurality of isolation structures respectively.

摘要翻译： 本公开的实施例包括形成集成电路的方法。 提供具有有源区和无源区的衬底。 在被动区域中形成多个沟槽。 每个沟槽的长度和宽度的均方根小于5um。 隔离材料沉积在衬底上以填充多个沟槽。 隔离材料被平坦化以形成多个隔离结构。 分别在有源区域和多个隔离结构上的衬底上形成多个硅栅叠层和至少一个硅电阻堆叠。

公开(公告)号：US08450216B2

公开(公告)日：2013-05-28

申请号：US12849601

申请日：2010-08-03

申请人： Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

发明人： Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/302

CPC分类号： H01L29/66545 ,  H01L21/0217 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7833

摘要： An exemplary structure for a field effect transistor according to at least one embodiment comprises a substrate comprising a surface; a gate structure comprising sidewalls and a top surface over the substrate; a spacer adjacent to the sidewalls of the gate structure; a first contact etch stop layer over the spacer and extending along the surface of the substrate; an interlayer dielectric layer adjacent to the first contact etch stop layer, wherein a top surface of the interlayer dielectric layer is coplanar with the top surface of the gate structure; and a second contact etch stop layer over the top surface of the gate structure.

摘要翻译： 根据至少一个实施例的用于场效应晶体管的示例性结构包括：包括表面的基板; 栅极结构，其包括在所述衬底上的侧壁和顶表面; 邻近所述栅极结构的侧壁的间隔物; 在所述间隔物上方的第一接触蚀刻停止层，并沿着所述衬底的表面延伸; 与所述第一接触蚀刻停止层相邻的层间电介质层，其中所述层间电介质层的顶表面与所述栅极结构的顶表面共面; 以及在栅极结构的顶表面上的第二接触蚀刻停止层。

公开(公告)号：US08664079B2

公开(公告)日：2014-03-04

申请号：US13316817

申请日：2011-12-12

申请人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/76

CPC分类号： H01L21/3081 ,  H01L21/76232

摘要： The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.

摘要翻译： 本公开涉及集成电路制造，更具体地涉及一种用于制造半导体器件的方法。 用于制造半导体器件的示例性方法包括提供衬底; 在衬底的前侧和后侧形成衬垫氧化物层; 在衬底的前侧和后侧上的衬垫氧化物层上形成硬掩模层; 以及在衬底的前侧的衬垫氧化物层之上使硬掩模层变薄。

公开(公告)号：US08525270B2

公开(公告)日：2013-09-03

申请号：US12713395

申请日：2010-02-26

申请人： Lee-Wee Teo ,  Ming Zhu ,  Chi-Ju Lee ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Harry-Hak-Lay Chuang

发明人： Lee-Wee Teo ,  Ming Zhu ,  Chi-Ju Lee ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/70

CPC分类号： H01L29/66545 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78

摘要： The methods and structures described are used to prevent protrusion of contact metal (such as W) horizontally into gate stacks of neighboring devices to affect the work functions of these neighboring devices. The metal gate under contact plugs that are adjacent to devices and share the (or are connected to) metal gate is defined and lined with a work function layer that has good step coverage to prevent contact metal from extruding into gate stacks of neighboring devices. Only modification to the mask layout for the photomask(s) used for removing dummy polysilicon is involved. No additional lithographical operation or mask is needed. Therefore, no modification to the manufacturing processes or additional substrate processing steps (or operations) is involved or required. The benefits of using the methods and structures described above may include increased device yield and performance.

摘要翻译： 所描述的方法和结构用于防止接触金属（例如W）水平地突出到相邻设备的门堆叠中，以影响这些相邻设备的功能。 定义了与设备相邻并且共享（或连接到）金属栅极的接触插塞下面的金属栅，并且衬有具有良好阶梯覆盖的功函数层，以防止接触金属挤出到相邻器件的栅极堆叠中。 仅涉及用于去除伪多晶硅的光掩模的掩模布局的修改。 不需要额外的光刻操作或掩模。 因此，不涉及制造工艺或附加的基板处理步骤（或操作）的修改。 使用上述方法和结构的好处可以包括提高器件产量和性能。

公开(公告)号：US08349678B2

公开(公告)日：2013-01-08

申请号：US12701824

申请日：2010-02-08

申请人： Harry-Hak-Lay Chuang ,  Lee-Wee Teo ,  Ming Zhu

发明人： Harry-Hak-Lay Chuang ,  Lee-Wee Teo ,  Ming Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/66659 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28185 ,  H01L29/41775 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78

摘要： A method of fabricating a laterally diffused metal oxide semiconductor (LDMOS) transistor includes forming a dummy gate over a substrate. A source and a drain are formed over the substrate on opposite sides of the dummy gate. A first silicide is formed on the source. A second silicide is formed on the drain so that an unsilicided region of at least one of the drain or the source is adjacent to the dummy gate. The unsilicided region of the drain provides a resistive region capable of sustaining a voltage load suitable for a high voltage LDMOS application. A replacement gate process is performed on the dummy gate to form a gate.

摘要翻译： 制造横向扩散的金属氧化物半导体（LDMOS）晶体管的方法包括在衬底上形成虚拟栅极。 在虚拟栅极的相对侧上的衬底上形成源极和漏极。 在源上形成第一硅化物。 在漏极上形成第二硅化物，使得至少一个漏极或源极的非硅化区域与虚拟栅极相邻。 漏极的非硅化区域提供能够承受适合于高电压LDMOS应用的电压负载的电阻区域。 在虚拟栅极上执行替换栅极处理以形成栅极。

公开(公告)号：US08143137B2

公开(公告)日：2012-03-27

申请号：US12706782

申请日：2010-02-17

申请人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/76

CPC分类号： H01L21/3081 ,  H01L21/76232

摘要： The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.

摘要翻译： 本公开涉及集成电路制造，更具体地涉及一种用于制造半导体器件的方法。 用于制造半导体器件的示例性方法包括提供衬底; 在衬底的前侧和后侧形成衬垫氧化物层; 在衬底的前侧和后侧上的衬垫氧化物层上形成硬掩模层; 以及在衬底的前侧的衬垫氧化物层之上使硬掩模层变薄。

公开(公告)号：US20110210403A1

公开(公告)日：2011-09-01

申请号：US12713395

申请日：2010-02-26

申请人： Lee-Wee TEO ,  Ming Zhu ,  Chi-Ju Lee ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Harry-Hak-Lay Chuang

发明人： Lee-Wee TEO ,  Ming Zhu ,  Chi-Ju Lee ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Harry-Hak-Lay Chuang

IPC分类号： H01L29/78 ,  H01L21/768

CPC分类号： H01L29/66545 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78

摘要： The methods and structures described are used to prevent protrusion of contact metal (such as W) horizontally into gate stacks of neighboring devices to affect the work functions of these neighboring devices. The metal gate under contact plugs that are adjacent to devices and share the (or are connected to) metal gate is defined and lined with a work function layer that has good step coverage to prevent contact metal from extruding into gate stacks of neighboring devices. Only modification to the mask layout for the photomask(s) used for removing dummy polysilicon is involved. No additional lithographical operation or mask is needed. Therefore, no modification to the manufacturing processes or additional substrate processing steps (or operations) is involved or required. The benefits of using the methods and structures described above may include increased device yield and performance.

摘要翻译： 所描述的方法和结构用于防止接触金属（例如W）水平地突出到相邻设备的门堆叠中，以影响这些相邻设备的功能。 定义了与设备相邻并且共享（或连接到）金属栅极的接触插塞下面的金属栅，并且衬有具有良好阶梯覆盖的功函数层，以防止接触金属挤出到相邻器件的栅极堆叠中。 仅涉及用于去除伪多晶硅的光掩模的掩模布局的修改。 不需要额外的光刻操作或掩模。 因此，不涉及制造工艺或附加的基板处理步骤（或操作）的修改。 使用上述方法和结构的好处可以包括提高器件产量和性能。

公开(公告)号：US08304842B2

公开(公告)日：2012-11-06

申请号：US12836106

申请日：2010-07-14

申请人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L21/768 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： The disclosure relates to integrated circuit fabrication, and more particularly to an interconnection structure for N/P metal gates. An exemplary structure for an interconnection structure comprises a first gate electrode having a first portion of a first work-function metal layer under a first portion of a signal metal layer; and a second gate electrode having a second portion of the first work-function metal layer interposed between a second work-function metal layer and a second portion of the signal metal layer, wherein the second portion of the signal metal layer is over the second portion of the first work-function metal layer, wherein the second portion of the signal metal layer and the first portion of the signal metal layer are continuous, and wherein a maximum thickness of the second portion of the signal metal layer is less than a maximum thickness of the first portion of the signal metal layer.

摘要翻译： 本公开涉及集成电路制造，更具体地涉及用于N / P金属栅极的互连结构。 用于互连结构的示例性结构包括在信号金属层的第一部分下方具有第一功函数金属层的第一部分的第一栅极电极; 以及第二栅电极，其具有插入在第二功函数金属层和信号金属层的第二部分之间的第一功函金属层的第二部分，其中信号金属层的第二部分在第二部分之上 的第一功函数金属层，其中信号金属层的第二部分和信号金属层的第一部分是连续的，并且其中信号金属层的第二部分的最大厚度小于最大厚度 的信号金属层的第一部分。