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56 条记录 (耗时 0.031 秒)

    Flash memory cell with a flair gate
    8.
    发明授权
    Flash memory cell with a flair gate 有权
    闪存单元，带有风格门

    公开(公告)号：US08367537B2

    公开(公告)日：2013-02-05

    申请号：US11801823

    申请日：2007-05-10

    申请人： Meng Ding ,  YouSeok Suh ,  Shenqing Fang ,  Kuo-Tung Chang

    发明人： Meng Ding ,  YouSeok Suh ,  Shenqing Fang ,  Kuo-Tung Chang

    IPC分类号： H01L21/283

    CPC分类号： H01L29/788 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/762 ,  H01L21/76224 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/792

    摘要： An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.

    摘要翻译： 本发明的实施例涉及一种形成存储单元的方法。 该方法包括蚀刻衬底中的沟槽并用氧化物填充沟槽以形成浅沟槽隔离（STI）区域。 与STI区域接触的衬底的有源区域的一部分形成位线STI边缘。 该方法还包括在衬底的有源区上方和STI区上形成栅极结构。 栅极结构具有基本上在衬底的有源区域的中心上方的第一宽度和基本上位于STI边缘的第二宽度，并且第二宽度大于第一宽度。

    Flash memory cell with a flair gate
    9.
    发明申请
    Flash memory cell with a flair gate 有权
    闪存单元，带有风格门

    公开(公告)号：US20080277712A1

    公开(公告)日：2008-11-13

    申请号：US11801823

    申请日：2007-05-10

    申请人： Meng Ding ,  YouSeok Suh ,  Shenqing Fang ,  Kuo-Tung Chang

    发明人： Meng Ding ,  YouSeok Suh ,  Shenqing Fang ,  Kuo-Tung Chang

    IPC分类号： H01L29/788 ,  H01L21/3205 ,  H01L21/76

    CPC分类号： H01L29/788 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/762 ,  H01L21/76224 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/792

    摘要： An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.

    摘要翻译： 本发明的实施例涉及一种形成存储单元的方法。 该方法包括蚀刻衬底中的沟槽并用氧化物填充沟槽以形成浅沟槽隔离（STI）区域。 与STI区域接触的衬底的有源区域的一部分形成位线STI边缘。 该方法还包括在衬底的有源区上方和STI区上形成栅极结构。 栅极结构具有基本上在衬底的有源区域的中心上方的第一宽度和基本上位于STI边缘的第二宽度，并且第二宽度大于第一宽度。

    Memory cell having enhanced high-K dielectric
    10.
    发明授权
    Memory cell having enhanced high-K dielectric 有权
    具有增强的高K电介质的存储单元

    公开(公告)号：US07365389B1

    公开(公告)日：2008-04-29

    申请号：US11008233

    申请日：2004-12-10

    申请人： Joong Jeon ,  Wei Zheng ,  Mark Randolph ,  Meng Ding ,  Hidehiko Shiraiwa

    发明人： Joong Jeon ,  Wei Zheng ,  Mark Randolph ,  Meng Ding ,  Hidehiko Shiraiwa

    IPC分类号： H01L29/792

    CPC分类号： H01L29/513 ,  H01L29/792

    摘要： A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory device may be efficiently erased using Fowler-Nordheim tunneling.

    摘要翻译： 半导体存储器件可以包括介于电荷存储层和控制栅之间的高K，高势垒高电介质材料的隔间电介质层。 利用这种隔间高K，高势垒高电介质就位，可以使用Fowler-Nordheim隧道有效地擦除存储器件。